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21.发明申请EMULATED ELECTRICALLY ERASABLE MEMORY HAVING AN ADDRESS RAM FOR DATA STORED IN FLASH MEMORY 审中-公开具有存储在闪存中的数据的地址RAM的模拟电可擦除存储器公开(公告)号：US20130346680A1
公开(公告)日：2013-12-26
申请号：US13530169
申请日：2012-06-22
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7207
摘要： A memory system comprises a memory controller, an address RAM coupled to the memory controller, and a non-volatile memory coupled to the memory controller. The non-volatile memory has an address portion and a data portion. The address portion of the non-volatile memory provides data portion addresses and data portion addresses of valid data to the memory controller. The memory controller loads the data portion addresses and stores them in the address RAM at locations defined by the data portion addresses of valid data into the address RAM. The memory controller uses the data portion addresses, and locations of data blocks within the address RAM, to locate the data blocks within the data portion of non-volatile memory. The memory controller uses the data portion addresses, and locations of the data block addresses within the address RAM, to locate data blocks within the data portion of non-volatile memory
摘要翻译： 存储器系统包括存储器控制器，耦合到存储器控制器的地址RAM以及耦合到存储器控制器的非易失性存储器。 非易失性存储器具有地址部分和数据部分。 非易失性存储器的地址部分向存储器控制器提供有效数据的数据部分地址和数据部分地址。 存储器控制器加载数据部分地址并将它们存储在地址RAM中，在由有效数据的数据部分地址定义的地址到地址RAM中。 存储器控制器使用数据部分地址和地址RAM内的数据块的位置来定位非易失性存储器的数据部分内的数据块。 存储器控制器使用数据部分地址和地址RAM内的数据块地址的位置来定位非易失性存储器的数据部分内的数据块
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22.发明申请MULTIPLE PARTITIONED EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY AND METHOD OF OPERATION 有权多重分区式电动可擦除（EEE）存储器和操作方法公开(公告)号：US20110271034A1
公开(公告)日：2011-11-03
申请号：US12769786
申请日：2010-04-29
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7203
摘要： A method and system wherein a volatile memory is partitioned to have a first percentage of address space dedicated to a first classification of data which is data that is expected to have greater than a predetermined number of times of being modified and a second percentage of address space dedicated to a second classification of data which is data that is expected to have less than the predetermined probability of being modified. Address assignment of data to be stored in the volatile memory is made on a basis of predicted change of the data. Memory addresses of the first and second percentages of address space are respectively assigned to first and second sections of nonvolatile memory. The memory addresses of the first percentage initially consume a smaller percentage of an address map of the first section than the memory addresses of the second percentage of the second section.
摘要翻译： 一种方法和系统，其中易失性存储器被分割成具有专用于数据的第一分类的第一百分比的地址空间，其是期望具有大于预定次数的被修改的数据和第二百分比的地址空间 专用于预期具有小于修改的预定概率的数据的数据的第二分类。 基于数据的预测变化，进行存储在易失性存储器中的数据的地址分配。 地址空间的第一和第二百分比的存储器地址分别被分配给非易失性存储器的第一和第二部分。 第一个百分比的存储器地址最初消耗第一部分的地址映射的百分比比第二部分的第二百分比的存储器地址小。
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公开(公告)号：US08793558B2
公开(公告)日：2014-07-29
申请号：US13595282
申请日：2012-08-27
IPC分类号： H03M13/00
CPC分类号： G06F11/1048 , G11C29/026 , G11C29/028
摘要： Adaptive error correction for non-volatile memories is disclosed that dynamically adjusts sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The adaptive error correction can also be used with respect to memories that are not non-volatile memories.
摘要翻译： 公开了用于非易失性存储器的自适应纠错，其动态地调整读出放大器读取检测窗口。 存储器控制电路使用纠错码（ECC）例程来检测使用这些ECC例程不可校正的位错误。 存储器控制电路然后动态地调整读出放大器读取检测窗口以允许确定正确的数据。 校正的数据可以输出到外部电路。 当随后的读取操作尝试访问先前遭受比特故障的地址位置时，也可以存储校正的数据以供稍后访问。 相对于不是非易失性存储器的存储器也可以使用自适应纠错。
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公开(公告)号：US20140059398A1
公开(公告)日：2014-02-27
申请号：US13595282
申请日：2012-08-27
CPC分类号： G06F11/1048 , G11C29/026 , G11C29/028
摘要： Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories.
摘要翻译： 公开了用于动态调整读出放大器读取检测窗口的非易失性存储器的自适应纠错的方法和系统。 存储器控制电路使用纠错码（ECC）例程来检测使用这些ECC例程不可校正的位错误。 存储器控制电路然后动态地调整读出放大器读取检测窗口以允许确定正确的数据。 校正的数据可以输出到外部电路。 当随后的读取操作尝试访问先前遭受比特故障的地址位置时，也可以存储校正的数据以供稍后访问。 所公开的方法和系统也可以用于不是非易失性存储器的存储器。
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25.发明授权Multiple partitioned emulated electrically erasable (EEE) memory and method of operation 有权多重划分仿真电可擦除（EEE）存储器和操作方法公开(公告)号：US08473710B2
公开(公告)日：2013-06-25
申请号：US12769786
申请日：2010-04-29
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7203
摘要： A method and system wherein a volatile memory is partitioned to have a first percentage of address space dedicated to a first classification of data which is data that is expected to have greater than a predetermined number of times of being modified and a second percentage of address space dedicated to a second classification of data which is data that is expected to have less than the predetermined probability of being modified. Address assignment of data to be stored in the volatile memory is made on a basis of predicted change of the data. Memory addresses of the first and second percentages of address space are respectively assigned to first and second sections of nonvolatile memory. The memory addresses of the first percentage initially consume a smaller percentage of an address map of the first section than the memory addresses of the second percentage of the second section.
摘要翻译： 一种方法和系统，其中易失性存储器被分割成具有专用于数据的第一分类的第一百分比的地址空间，其是期望具有大于预定次数的被修改的数据和第二百分比的地址空间 专用于预期具有小于修改的预定概率的数据的数据的第二分类。 基于数据的预测变化，进行存储在易失性存储器中的数据的地址分配。 地址空间的第一和第二百分比的存储器地址分别被分配给非易失性存储器的第一和第二部分。 第一个百分比的存储器地址最初消耗第一部分的地址映射的百分比比第二部分的第二百分比的存储器地址小。
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26.发明申请Digital Control For Regulation Of Program Voltages For Non-Volatile Memory (NVM) Systems 有权用于非易失性存储器（NVM）系统的程序电压调节的数字控制公开(公告)号：US20150235704A1
公开(公告)日：2015-08-20
申请号：US14185454
申请日：2014-02-20
摘要： Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.
摘要翻译： 公开了用于数字控制以调节非易失性存储器（NVM）系统的编程电压的方法和系统。 所公开的实施例基于与要编程的单元相关联的参数来动态地调节编程电压，以便考虑在编程电压分配线内发生的IR（电流 - 电阻）电压降。 也可以通过这些动态调整来考虑其他电压变化。 要编程的单元的参数可以包括例如要编程的单元的单元地址位置，要编程的单元的数量，和/或与要编程的单元相关联的其它期望的参数。 所公开的实施例使用基于单元参数从查找表获得的数字控制值来调整由用于编程所选择的单元的电压产生电路块产生的输出电压，从而将程序输出电压电平调谐到预定的期望电平。
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27.发明授权Sector-based regulation of program voltages for non-volatile memory (NVM) systems 有权基于部门的非易失性存储器（NVM）系统的程序电压调节公开(公告)号：US09013927B1
公开(公告)日：2015-04-21
申请号：US14050962
申请日：2013-10-10
CPC分类号： G11C29/021 , G11C5/145 , G11C8/12 , G11C16/08 , G11C16/12 , G11C16/30 , G11C29/028 , G11C2029/1202
摘要： Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.
摘要翻译： 公开了用于非易失性存储器（NVM）系统的用于基于扇区的程序电压调节的方法和系统。 所公开的实施例基于从扇区返回电压产生的反馈信号来调节NVM单元的编程电压，所述反馈信号与将编程电压相关联的程序电压驱动到选定扇区内的NVM单元NVM阵列。 因此，编程电压分配线中的IR（电流 - 电阻）电压损失导致的编程电压电平下降被有效地解决。 程序电压的基于扇区的调节在编程的单元有效地保持所需的编程电压，而不管正在被访问的扇区用于编程和正被编程的单元的数量。 扇区返回电压也可以与本地编程电压一起使用，为电压产生电路提供两步反馈调节。 也可以使用测试输入和/或输出焊盘提供测试模式配置。
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28.发明申请SECTOR-BASED REGULATION OF PROGRAM VOLTAGES FOR NON-VOLATILE MEMORY (NVM) SYSTEMS 有权针对非易失性存储器（NVM）系统的程序电压的基于行业的规范公开(公告)号：US20150103602A1
公开(公告)日：2015-04-16
申请号：US14050962
申请日：2013-10-10
IPC分类号： G11C16/10
CPC分类号： G11C29/021 , G11C5/145 , G11C8/12 , G11C16/08 , G11C16/12 , G11C16/30 , G11C29/028 , G11C2029/1202
摘要： Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.
摘要翻译： 公开了用于非易失性存储器（NVM）系统的用于基于扇区的程序电压调节的方法和系统。 所公开的实施例基于从扇区返回电压产生的反馈信号来调节NVM单元的编程电压，所述反馈信号与将编程电压相关联的程序电压驱动到选定扇区内的NVM单元NVM阵列。 因此，编程电压分配线中的IR（电流 - 电阻）电压损失导致的编程电压电平下降被有效地解决。 程序电压的基于扇区的调节在编程的单元有效地保持所需的编程电压，而不管正在被访问的扇区用于编程以及正被编程的单元的数量。 扇区返回电压也可以与本地编程电压一起使用，为电压产生电路提供两步反馈调节。 也可以使用测试输入和/或输出焊盘提供测试模式配置。
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公开(公告)号：US20130265828A1
公开(公告)日：2013-10-10
申请号：US13441335
申请日：2012-04-06
IPC分类号： G11C16/10
CPC分类号： G11C16/30 , G11C5/145 , G11C8/08 , G11C16/3454
摘要： A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle.
摘要翻译： 半导体存储器件包括非易失性存储器，存储器控制器和电荷泵系统。 存储器控制器在执行第一编程周期之前为非易失性存储器的第一多个存储器单元的第一编程周期建立第一参数。 电荷泵系统包括多个电荷泵并提供用于执行第一程序循环的第一编程脉冲。 第一编程脉冲通过根据第一参数选择在第一编程周期期间启用多个电荷泵中的哪一个并在第一编程周期期间被禁用来提供。
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公开(公告)号：US08341372B2
公开(公告)日：2012-12-25
申请号：US12769795
申请日：2010-04-29
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0804 , G06F2212/401 , G06F2212/7203
摘要： A system has an emulation memory having a plurality of sectors for storing information. A controller calculates a number of addresses used divided by a number of valid records in a predetermined address range of the emulation memory. An amount of remaining addresses in a currently used space of the emulation memory which have not been used to store information is calculated. A determination is made whether the calculation is greater than a first predetermined number and whether the amount of remaining addresses is greater than a second predetermined number. If both the fraction is greater than the first predetermined number and the amount of remaining addresses is greater than the second predetermined number, any subsequent update requests are responded to using the currently used space of the emulation memory. Otherwise a compression of the emulation memory is required by copying valid data to an available sector.
摘要翻译： 系统具有具有用于存储信息的多个扇区的仿真存储器。 控制器计算所使用的地址数量除以仿真存储器的预定地址范围中的有效记录数。 计算未被用于存储信息的仿真存储器的当前使用空间中的剩余地址的量。 确定计算是否大于第一预定数量，以及剩余地址的数量是否大于第二预定数量。 如果分数都大于第一预定数量，并且剩余地址的量大于第二预定数量，则使用当前使用的仿真存储器的空间来响应任何后续的更新请求。 否则，通过将有效数据复制到可用扇区，需要对仿真存储器进行压缩。
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