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1.发明申请EMULATED ELECTRICALLY ERASABLE MEMORY HAVING AN ADDRESS RAM FOR DATA STORED IN FLASH MEMORY 审中-公开具有存储在闪存中的数据的地址RAM的模拟电可擦除存储器公开(公告)号：US20130346680A1
公开(公告)日：2013-12-26
申请号：US13530169
申请日：2012-06-22
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7207
摘要： A memory system comprises a memory controller, an address RAM coupled to the memory controller, and a non-volatile memory coupled to the memory controller. The non-volatile memory has an address portion and a data portion. The address portion of the non-volatile memory provides data portion addresses and data portion addresses of valid data to the memory controller. The memory controller loads the data portion addresses and stores them in the address RAM at locations defined by the data portion addresses of valid data into the address RAM. The memory controller uses the data portion addresses, and locations of data blocks within the address RAM, to locate the data blocks within the data portion of non-volatile memory. The memory controller uses the data portion addresses, and locations of the data block addresses within the address RAM, to locate data blocks within the data portion of non-volatile memory
摘要翻译： 存储器系统包括存储器控制器，耦合到存储器控制器的地址RAM以及耦合到存储器控制器的非易失性存储器。 非易失性存储器具有地址部分和数据部分。 非易失性存储器的地址部分向存储器控制器提供有效数据的数据部分地址和数据部分地址。 存储器控制器加载数据部分地址并将它们存储在地址RAM中，在由有效数据的数据部分地址定义的地址到地址RAM中。 存储器控制器使用数据部分地址和地址RAM内的数据块的位置来定位非易失性存储器的数据部分内的数据块。 存储器控制器使用数据部分地址和地址RAM内的数据块地址的位置来定位非易失性存储器的数据部分内的数据块
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公开(公告)号：US20110271035A1
公开(公告)日：2011-11-03
申请号：US12769795
申请日：2010-04-29
CPC分类号： G06F12/0246 , G06F12/0804 , G06F2212/401 , G06F2212/7203
摘要： A system has an emulation memory having a plurality of sectors for storing information. A controller calculates a number of addresses used divided by a number of valid records in a predetermined address range of the emulation memory. An amount of remaining addresses in a currently used space of the emulation memory which have not been used to store information is calculated. A determination is made whether the calculation is greater than a first predetermined number and whether the amount of remaining addresses is greater than a second predetermined number. If both the fraction is greater than the first predetermined number and the amount of remaining addresses is greater than the second predetermined number, any subsequent update requests are responded to using the currently used space of the emulation memory. Otherwise a compression of the emulation memory is required by copying valid data to an available sector.
摘要翻译： 系统具有具有用于存储信息的多个扇区的仿真存储器。 控制器计算所使用的地址数量除以仿真存储器的预定地址范围中的有效记录数。 计算未被用于存储信息的仿真存储器的当前使用空间中的剩余地址的量。 确定计算是否大于第一预定数量，以及剩余地址的数量是否大于第二预定数量。 如果分数都大于第一预定数量，并且剩余地址的量大于第二预定数量，则使用当前使用的仿真存储器的空间来响应任何后续的更新请求。 否则，通过将有效数据复制到可用扇区，需要对仿真存储器进行压缩。
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公开(公告)号：US20130268717A1
公开(公告)日：2013-10-10
申请号：US13442028
申请日：2012-04-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7209 , G11C16/10
摘要： A semiconductor memory device comprises a volatile memory and a non-volatile memory including a plurality of sectors. Each of the plurality of sectors configured to store a sector status indicator and a plurality of data records. A control module is coupled to the non-volatile memory and the volatile memory. The control module manages the sectors by scanning the sectors to identify the records with invalid data; changing the status indicator of a particular sector when all of the records in the particular sector are invalid, and discontinuing scanning the particular sector while all of the records in the particular sector are invalid.
摘要翻译： 半导体存储器件包括易失性存储器和包括多个扇区的非易失性存储器。 多个扇区中的每一个被配置为存储扇区状态指示符和多个数据记录。 控制模块耦合到非易失性存储器和易失性存储器。 控制模块通过扫描扇区来管理扇区，以识别具有无效数据的记录; 当特定扇区中的所有记录无效时，改变特定扇区的状态指示符，并且在特定扇区中的所有记录无效时停止扫描特定扇区。
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公开(公告)号：US20120005403A1
公开(公告)日：2012-01-05
申请号：US12826814
申请日：2010-06-30
CPC分类号： G06F11/073 , G06F11/0763 , G06F11/0793 , G06F12/0246
摘要： In a system having an emulation memory having a first sector of non-volatile memory for storing information, wherein the non-volatile memory includes a plurality of records, a method includes determining if a last record written of the plurality of records is a compromised record; if the last record written is not a compromised record, performing a next write to a record of the plurality of records that is next to the last record written; and if the last record written is a comprised record: determining an address of the compromised record; writing valid data for the address of the compromised record into the record of the plurality of records that is next to the compromised record; and writing data into a record that is next to the record of the plurality of records that is next to the compromised record.
摘要翻译： 在具有模拟存储器的系统中，具有用于存储信息的非易失性存储器的第一扇区，其中所述非易失性存储器包括多个记录，所述方法包括确定所述多个记录中写入的最后记录是否是受损记录 ; 如果写入的最后一个记录不是受损记录，则对写入的最后记录旁边的多个记录执行下一次写入; 并且如果写入的最后一个记录是包含的记录：确定受损记录的地址; 将受损记录的地址的有效数据写入到被破坏的记录旁边的多个记录的记录中; 并将数据写入与所述受损记录旁边的所述多个记录的记录相邻的记录。
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5.发明申请MULTIPLE PARTITIONED EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY AND METHOD OF OPERATION 有权多重分区式电动可擦除（EEE）存储器和操作方法公开(公告)号：US20110271034A1
公开(公告)日：2011-11-03
申请号：US12769786
申请日：2010-04-29
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7203
摘要： A method and system wherein a volatile memory is partitioned to have a first percentage of address space dedicated to a first classification of data which is data that is expected to have greater than a predetermined number of times of being modified and a second percentage of address space dedicated to a second classification of data which is data that is expected to have less than the predetermined probability of being modified. Address assignment of data to be stored in the volatile memory is made on a basis of predicted change of the data. Memory addresses of the first and second percentages of address space are respectively assigned to first and second sections of nonvolatile memory. The memory addresses of the first percentage initially consume a smaller percentage of an address map of the first section than the memory addresses of the second percentage of the second section.
摘要翻译： 一种方法和系统，其中易失性存储器被分割成具有专用于数据的第一分类的第一百分比的地址空间，其是期望具有大于预定次数的被修改的数据和第二百分比的地址空间 专用于预期具有小于修改的预定概率的数据的数据的第二分类。 基于数据的预测变化，进行存储在易失性存储器中的数据的地址分配。 地址空间的第一和第二百分比的存储器地址分别被分配给非易失性存储器的第一和第二部分。 第一个百分比的存储器地址最初消耗第一部分的地址映射的百分比比第二部分的第二百分比的存储器地址小。
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公开(公告)号：US20150348595A1
公开(公告)日：2015-12-03
申请号：US14287463
申请日：2014-05-27
CPC分类号： G11C5/06 , G11C5/025 , G11C5/063 , G11C5/14 , G11C13/0004 , G11C13/0011 , G11C13/0021 , G11C13/0023 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/74 , G11C2213/79 , G11C2213/82
摘要： A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.
摘要翻译： 存储单元包括具有耦合到第一电源轨的阴极和耦合到内部节点的阳极的第一双向电阻元件，具有耦合到内部节点的阴极的第二双向电阻元件和耦合到内部节点的阳极 第二电源轨，以及具有耦合到所述内部节点的控制电极的第一晶体管，耦合到第一位线的第一电流电极和耦合到第三电力轨的第二电流电极。
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7.发明申请ERASING A NON-VOLATILE MEMORY (NVM) SYSTEM HAVING ERROR CORRECTION CODE (ECC) 有权擦除具有错误修正代码（ECC）的非易失性存储器（NVM）系统公开(公告)号：US20130290808A1
公开(公告)日：2013-10-31
申请号：US13459344
申请日：2012-04-30
申请人： Fuchen Mu , Frank K. Baker, JR. , Chen He
发明人： Fuchen Mu , Frank K. Baker, JR. , Chen He
CPC分类号： G11C16/16 , G11C16/3481
摘要： A method of erasing a non-volatile semiconductor memory device comprising determining a number of bit cells that failed to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.
摘要翻译： 一种擦除非易失性半导体存储器件的方法，包括在擦除操作期间确定不能擦除验证的位单元数目。 位单元包括在位单元阵列中的位单元的子集中。 该方法还包括确定是否先前对位单元的子集执行纠错码（ECC）校正。 如果在预定数量的擦除脉冲之后无法擦除验证的比特单元的数量低于阈值并且还没有对比特单元的子集执行ECC校正，则擦除操作被认为是成功的。
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公开(公告)号：US20130267072A1
公开(公告)日：2013-10-10
申请号：US13780591
申请日：2013-02-28
IPC分类号： H01L21/82
CPC分类号： H01L21/82 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/7881
摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.
摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中，在第一热生长含氧层上形成NVM单元的多晶硅选择栅极，在逻辑区域中，在高k电介质和多晶硅上形成功函数设定材料 在工作功能设置材料上形成虚拟门。 在形成第一热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 多晶硅虚拟栅极由金属栅极代替。 在形成电荷存储区域的同时形成NVM单元时，保护逻辑晶体管。
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公开(公告)号：US20130178027A1
公开(公告)日：2013-07-11
申请号：US13780574
申请日：2013-02-28
IPC分类号： H01L29/66
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/42348 , H01L29/4933 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66833 , H01L29/7881
摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.
摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中的第一热生长含氧层上形成NVM单元的多晶硅选择栅极，并且在逻辑区域中的第二热生长含氧层上形成多晶硅虚拟栅极。 在形成第一和第二热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 第二热生长含氧层和虚拟栅极被金属栅极和高k电介质代替。 保护逻辑晶体管，同时形成NVM单元，包括形成电荷存储层。
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公开(公告)号：US20160035415A1
公开(公告)日：2016-02-04
申请号：US14448174
申请日：2014-07-31
CPC分类号： G11C13/004 , G11C8/14 , G11C13/0028 , G11C13/003 , G11C13/0069 , G11C2013/0071 , G11C2213/74 , G11C2213/79 , G11C2213/82
摘要： A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail.
摘要翻译： 存储单元包括具有直接连接到第一电源轨的第一端子和耦合到内部节点的第二端子的单个双向电阻存储元件（BRME）; 以及第一晶体管，其具有耦合到所述内部节点的控制电极，以及耦合到第一位线的第一电流电极和耦合到由读取字线和所述第一电力轨道组成的组中的一个的第二电流电极。
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