公开(公告)号：US20240397831A1

公开(公告)日：2024-11-28

申请号：US18402434

申请日：2024-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho Lee ,  Junho Park ,  Byoungjae Bae

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/01

Abstract: A semiconductor device includes data storage patterns provided on a substrate and spaced apart from each other in first and second directions parallel to a top surface of the substrate, first cell conductive lines provided on the data storage patterns, extended in the first direction, and spaced apart from each other in the second direction, each of the first cell conductive lines being connected to corresponding ones of the data storage patterns, which are spaced apart from each other in the first direction, and cell via contacts spaced apart from each other in the first direction, between the first cell conductive lines. Each of the cell via contacts between the first cell conductive lines may be extended in the second direction and may be connected to dummy data storage patterns of the data storage patterns, which are spaced apart from each other in the second direction.

公开(公告)号：US11557631B2

公开(公告)日：2023-01-17

申请号：US17088168

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Ilmok Park ,  Junhee Lim

IPC: H01L27/24 ,  H01L27/1157 ,  G11C11/16 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/11575 ,  G11C14/00 ,  G11C5/02 ,  G11C16/04

Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

公开(公告)号：US11437432B2

公开(公告)日：2022-09-06

申请号：US17028034

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Woojin Kim

IPC: H01L27/22 ,  H01L23/522 ,  H01L21/768 ,  H01L43/12

Abstract: An embedded device includes a first insulation layer, a second insulation layer on the first insulation layer, a lower electrode contact in the first insulation layer in a first region, a first structure, having a lower electrode, a magnetic tunnel junction, and an upper electrode, in the second insulation layer and contacting the lower electrode contact, a first metal wiring structure through the first and second insulation layers in a second region, a third insulation layer on the second insulation layer, a bit line structure through the third insulation layer and the second insulation layer in the first region, the bit line structure having a first height and contacting the upper electrode, and a second metal wiring structure through the third insulation layer in the second region, the second metal wiring structure contacting the first metal wiring structure, and having a second height lower than the first height.

公开(公告)号：US11361798B2

公开(公告)日：2022-06-14

申请号：US16411106

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Junhee Lim ,  Hongsoo Kim ,  Chang-hoon Jeon

IPC: G11C5/06 ,  G11C16/04 ,  G11C11/16 ,  H01L25/18 ,  H01L27/22 ,  H01L27/11573 ,  H01L43/10 ,  H01L27/1157 ,  G11C13/00 ,  G11C11/00 ,  H01L27/11582

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.