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公开(公告)号：US20250157516A1
公开(公告)日：2025-05-15
申请号：US18925376
申请日：2024-10-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongjae Lee , Kilho Lee , Ung Hwan Pi
Abstract: A magnetic memory device comprising a substrate, a first dielectric pattern on the substrate, a dielectric pillar including a penetration part that penetrates the first dielectric pattern and a protrusion part that protrudes above a top surface of the first dielectric pattern, a first magnetic pattern between the first dielectric pattern and the dielectric pillar and including a first part that surrounds a lateral surface of the penetration part and a second part that surrounds a lateral surface of the protrusion part, a second magnetic pattern on the first dielectric pattern and surrounding a lateral surface of the second part, and a tunnel barrier pattern on the first dielectric pattern and between the second part and the second magnetic pattern. The first magnetic pattern extends in a third direction perpendicular to a top surface of the substrate.
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公开(公告)号：US20250151627A1
公开(公告)日：2025-05-08
申请号：US18671519
申请日：2024-05-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kilho Lee , Yongjae Kim , Kiseok Suh
Abstract: A method of manufacturing a magnetoresistive memory device includes: forming, sequentially, a magnetic tunnel junction (MTJ) structure and a metal layer on a substrate in first and second cell regions; performing a first oxidation process on the metal layer in the first and second cell regions to form a first metal oxide layer; performing an ion implantation process on the first metal oxide layer in the first cell region to form a second metal oxide layer while the first metal oxide layer is exposed in the second cell region; and patterning the MTJ structure, the first and second metal oxide layers to form a first memory element including a first MTJ structure and the second metal oxide layer in the first cell region, and to form a second memory element including a second MTJ structure and the first metal oxide layer in the second cell region.
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公开(公告)号：US11659719B2
公开(公告)日：2023-05-23
申请号：US17381768
申请日：2021-07-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kilho Lee , Gwanhyeob Koh
CPC classification number: H01L27/228 , G11C11/02 , G11C11/5614
Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.
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公开(公告)号：US11121175B2
公开(公告)日：2021-09-14
申请号：US16848010
申请日：2020-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kilho Lee , Gwanhyeob Koh
Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.
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5.发明公开公开(公告)号：US20240203686A1
公开(公告)日：2024-06-20
申请号：US18366355
申请日：2023-08-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kilho Lee
IPC: H01J37/20
CPC classification number: H01J37/20 , H01J2237/20214 , H01J2237/20278 , H01J2237/208
Abstract: A guide pin includes a support part and a frictional column coupled to the support part, and the support part includes a lower support member including a screw structure on an outer surface thereof, and an upper support member on the lower support member. The frictional column surrounds an outer surface of the upper support member. A hardness of the frictional column is lower than a hardness of the support part.
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Patent Agency Ranking
公开(公告)号：US10897006B2
公开(公告)日：2021-01-19
申请号：US16286718
申请日：2019-02-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kilho Lee , Gwanhyeob Koh , Yongjae Kim , Yoonjong Song
Abstract: A magnetic memory device including a substrate including a cell region and a peripheral circuit region; a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate; interconnection lines in the first interlayer insulating layer; a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines; a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines; and a data storage pattern on the bottom electrode contact, wherein the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact.
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公开(公告)号：US10693055B2
公开(公告)日：2020-06-23
申请号：US16202360
申请日：2018-11-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kilho Lee , Gwanhyeob Koh , Yoonjong Song
Abstract: Magnetic random access memory (MRAM) devices are provided. The MRAM devices may include a magnetic tunnel junction (MTJ) including a free layer and a pinned layer sequentially stacked in a vertical direction and a conductive layer adjacent to the free layer of the MTJ. The conductive layer may include a horizontal portion and first and second protruding portions that protrude away from the horizontal portion and are spaced apart from each other in a horizontal direction that is perpendicular to the vertical direction. A side of the free layer and a side of the horizontal portion may form a straight side.
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公开(公告)号：US09865800B2
公开(公告)日：2018-01-09
申请号：US15404325
申请日：2017-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhee Han , Kilho Lee , Yoonjong Song
CPC classification number: H01L43/02 , G11C11/161 , H01L27/222 , H01L27/224 , H01L27/226 , H01L43/08 , H01L43/12
Abstract: Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.
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公开(公告)号：US09246083B2
公开(公告)日：2016-01-26
申请号：US14498465
申请日：2014-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kilho Lee , Ki Joon Kim , Se Woong Park
IPC: H01L21/8238 , H01L43/12 , H01L29/82 , H01L27/108 , H01L27/22
CPC classification number: H01L43/12 , H01L27/10888 , H01L27/222 , H01L27/228 , H01L29/82
Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.
Abstract translation: 存储器件及其制造方法包括：包括单元区域和外围电路区域的衬底，在单元区域上的数据存储，在数据存储器上并耦合到数据存储器的第一位线，耦合到外围电路区域上的外围晶体管的第一触点 以及在第一触点上并耦合到第一触点的第二位线。 第二位线可以各自具有低于数据存储器的最低表面的最下表面。
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公开(公告)号：US20240389352A1
公开(公告)日：2024-11-21
申请号：US18400741
申请日：2023-12-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kilho Lee
IPC: H10B61/00
Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a wiring structure on the cell and peripheral regions, a lower insulating layer on the wiring structure on the cell and peripheral regions, data storage patterns on the lower insulating layer on the cell region, a cell insulating layer on the lower insulating layer on the cell region and covering the data storage patterns, including cell extending portions extending above the lower insulating layer on the peripheral region in a first direction, the cell extending portions spaced apart from each other in a second direction, and a peripheral insulating layer on the lower insulating layer on the peripheral region and including a material different from that of the cell insulating layer. The peripheral insulating layer extends between the cell extending portions and is in contact with a side surface of the cell insulating layer.
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