公开(公告)号：US10276583B2

公开(公告)日：2019-04-30

申请号：US15730045

申请日：2017-10-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Fumitaka Amano ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Fei Zhou

IPC: H01L27/11563 ,  H01L27/11578 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/441 ,  H01L21/443 ,  H01L21/768 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11534 ,  H01L27/11556 ,  H01L27/11573 ,  H01L29/49

Abstract: Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. A metal silicide layer and metal portion are formed in the backside recesses to form the word lines including a metal portion, a metal silicide layer, and optionally, a silicon-containing layer.

公开(公告)号：US12035535B2

公开(公告)日：2024-07-09

申请号：US17237447

申请日：2021-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Rahul Sharangpani

IPC: H10B51/20 ,  H01L29/76 ,  H10B41/27 ,  H10B43/27 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/24

CPC classification number: H10B51/20 ,  H01L29/7606 ,  H10B41/27 ,  H10B43/27 ,  H01L29/16 ,  H01L29/1606 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/24

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and a vertical stack of discrete memory material portions laterally surrounding the vertical word line.

公开(公告)号：US11996462B2

公开(公告)日：2024-05-28

申请号：US17097841

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati Prasad ,  Joyeeta Nag ,  Seung-Yeul Yang ,  Adarsh Rajashekhar ,  Raghuveer S. Makala

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L21/31155 ,  H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/20 ,  H10B51/30

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US20240130137A1

公开(公告)日：2024-04-18

申请号：US18233628

申请日：2023-08-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik Sondhi ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Rahul Sharangpani ,  Fei Zhou

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/40

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/40

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers. The discrete ferroelectric material portions protrude inward into the memory opening relative to vertical sidewalls of the insulating layers.

公开(公告)号：US20220130853A1

公开(公告)日：2022-04-28

申请号：US17082629

申请日：2020-10-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L29/04 ,  H01L29/45 ,  H01L21/285 ,  H01L21/02 ,  H01L25/00

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.

公开(公告)号：US11309301B2

公开(公告)日：2022-04-19

申请号：US16886221

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Adarsh Rajashekhar

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

公开(公告)号：US11302716B2

公开(公告)日：2022-04-12

申请号：US16876816

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli Zhang ,  Fei Zhou ,  Rahul Sharangpani ,  Adarsh Rajashekhar ,  Seung-Yeul Yang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11585 ,  H01L23/528 ,  H01L23/522

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US11145628B1

公开(公告)日：2021-10-12

申请号：US16825397

申请日：2020-03-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Senaka Kanakamedala ,  Fei Zhou

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

公开(公告)号：US20210036019A1

公开(公告)日：2021-02-04

申请号：US16910638

申请日：2020-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Seung-Yeul Yang

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers.

公开(公告)号：US20200279862A1

公开(公告)日：2020-09-03

申请号：US16290277

申请日：2019-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Rahul Sharangpani

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.