公开(公告)号：US20210082515A1

公开(公告)日：2021-03-18

申请号：US17102712

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/1157

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

公开(公告)号：US20200312410A1

公开(公告)日：2020-10-01

申请号：US16898145

申请日：2020-06-10

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep ,  Zhengyi Zhang

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/04

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

公开(公告)号：US20200265897A1

公开(公告)日：2020-08-20

申请号：US16280297

申请日：2019-02-20

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11578 ,  H01L27/1157

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

公开(公告)号：US10706941B1

公开(公告)日：2020-07-07

申请号：US16371289

申请日：2019-04-01

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep ,  Zhengyi Zhang

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

公开(公告)号：US10276248B1

公开(公告)日：2019-04-30

申请号：US15849019

申请日：2017-12-20

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34

Abstract: Techniques for reducing a downshift in the threshold voltage of a select gate transistor of a memory device. Due to an electric field in a NAND string, holes can move in a charge-trapping layer from a dummy memory cell to a select gate transistor and combine with electrons in the transistor, reducing the threshold voltage. In one approach, the electric field is reduced at the end of a sensing operation by ramping down the voltage of the dummy memory cells before ramping down the voltage of the select gate transistors. The ramp down of the voltage of the selected memory cells can occur after ramping down the voltage of the dummy memory cells and before ramping down of the voltage of the select gate transistors. A further option involves elevating the voltage of the select gate transistors before it is ramped down.

公开(公告)号：US20170345470A1

公开(公告)日：2017-11-30

申请号：US15163171

申请日：2016-05-24

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Vinh Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C7/14 ,  G11C7/04 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/14 ,  G11C7/04 ,  G11C7/062 ,  G11C7/22 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582

Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.

公开(公告)号：US09830963B1

公开(公告)日：2017-11-28

申请号：US15163171

申请日：2016-05-24

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Vinh Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C7/14 ,  G11C7/04 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/14 ,  G11C7/04 ,  G11C7/062 ,  G11C7/22 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582

Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.