-
公开(公告)号：US11024387B2
公开(公告)日：2021-06-01
申请号：US17102712
申请日：2020-11-24
发明人： Ching-Huang Lu , Ashish Baraskar , Vinh Diep
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34 , H01L27/11582 , H01L27/1157 , H01L27/11565 , G11C11/56 , G11C16/26
摘要： Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.
-
2.发明申请公开(公告)号：US20200335168A1
公开(公告)日：2020-10-22
申请号：US16922037
申请日：2020-07-07
发明人： Ching-Huang Lu , Ashish Baraskar , Vinh Diep
IPC分类号： G11C16/14 , G11C16/34 , H01L27/1157 , G11C16/04 , H01L27/11578
摘要： Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.
-
3.发明申请公开(公告)号：US20200243141A1
公开(公告)日：2020-07-30
申请号：US16847377
申请日：2020-04-13
发明人： Ching-Huang Lu , Ashish Baraskar , Vinh Diep
IPC分类号： G11C16/10 , H01L27/11582 , G11C16/04 , H01L27/1157 , G11C16/34
摘要： Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.
-
公开(公告)号：US10446244B1
公开(公告)日：2019-10-15
申请号：US15948761
申请日：2018-04-09
发明人： Vinh Diep , Ching-Huang Lu , Zhengyi Zhang , Yingda Dong
摘要： Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.
-
5.发明申请公开(公告)号：US20190259462A1
公开(公告)日：2019-08-22
申请号：US15900093
申请日：2018-02-20
发明人： Ching-Huang Lu , Vinh Diep
摘要： Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors.
-
公开(公告)号：US09922705B1
公开(公告)日：2018-03-20
申请号：US15621222
申请日：2017-06-13
发明人： Vinh Diep , Xuehong Yu , Zhengyi Zhang , Yingda Dong
CPC分类号： G11C11/5635 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C2216/28
摘要： A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when the voltages of the drain and source ends of a memory string are increased to an erase level which charges up the channel. In one approach, the voltage of the word line which is adjacent to a select gate line is temporarily increased. Another approach builds off the first approach by temporarily increasing the voltage of the select gate line at the same time as the increase in the word line voltage.
-
公开(公告)号：US10566059B2
公开(公告)日：2020-02-18
申请号：US16014028
申请日：2018-06-21
发明人： Vinh Diep , Ching Huang Lu , Henry Chin , Changyuan Chen
IPC分类号： G11C11/34 , G11C16/04 , H01L27/1157 , H01L29/423 , H01L27/11573 , H01L29/792 , H01L27/11582
摘要： Systems, methods, and devices of the various embodiments provide both “string-sharing” drain select gate electrodes and “string-selective” drain select gate electrodes in vertical NAND strings. Various embodiments may provide two or more vertical NAND strings sharing a common drain select gate electrode while also having separate additional drain select gate electrodes not electrically connected across the two or more vertical NAND strings.
-
公开(公告)号：US10482981B2
公开(公告)日：2019-11-19
申请号：US15900093
申请日：2018-02-20
发明人： Ching-Huang Lu , Vinh Diep
IPC分类号： G11C16/04 , G11C16/34 , G11C16/30 , G11C16/26 , G11C16/32 , G11C16/08 , G11C11/56 , G11C16/24 , G11C16/10
摘要： Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors.
-
公开(公告)号：US10068651B1
公开(公告)日：2018-09-04
申请号：US15621215
申请日：2017-06-13
发明人： Vinh Diep , Wei Zhao , Ashish Baraskar , Ching-Huang Lu , Yingda Dong
摘要： A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation. A pre-charge operation occurs in which a channel voltage is increased to a positive level. This reduces a channel gradient which can lead to a disturb of the select gate transistors. One approach involves applying a voltage at an intermediate level to the source and/or drain ends of the memory strings, before increasing the voltage from the intermediate level to a peak erase level. Another approach involves driving the word line voltages at a negative level and then at a higher level to down couple and then up couple the channel voltages. The techniques may be adjusted depending on whether the word lines are at a positive floating voltage at a start of the erase operation, and based on a level of the floating voltage.
-
10.发明授权公开(公告)号：US11037640B2
公开(公告)日：2021-06-15
申请号：US16900015
申请日：2020-06-12
发明人： Ashish Baraskar , Ching-Huang Lu , Vinh Diep , Yingda Dong
摘要： Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.036 秒)
