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公开(公告)号：US09959932B1
公开(公告)日：2018-05-01
申请号：US15437718
申请日：2017-02-21
发明人： Zhengyi Zhang , Yingda Dong , James Kai , Johann Alsmeier
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/3459
摘要： A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.
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公开(公告)号：US10446244B1
公开(公告)日：2019-10-15
申请号：US15948761
申请日：2018-04-09
发明人： Vinh Diep , Ching-Huang Lu , Zhengyi Zhang , Yingda Dong
摘要： Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.
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公开(公告)号：US10431313B2
公开(公告)日：2019-10-01
申请号：US15923064
申请日：2018-03-16
发明人： Zhengyi Zhang , Yingda Dong , James Kai , Johann Alsmeier
摘要： A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.
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公开(公告)号：US09984760B1
公开(公告)日：2018-05-29
申请号：US15403710
申请日：2017-01-11
发明人： Zhengyi Zhang , Liang Pang , Yingda Dong
CPC分类号： G11C16/3431 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459
摘要： A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel of the string is charged up from a source end of the string. However, there is a delay in charging up a drain end of the channel. A voltage detector connected to a bit line detects when a drain end of the channel reaches a reference voltage. When the reference voltage is reached, a voltage of the select gate transistor at the drain end of the string can be floated. This avoids unintentional programming of the select gate transistor which could otherwise occur if the voltage was floated to soon. Also, a substrate voltage may be ramped up to a first detected level before being ramped up to a second, final level.
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公开(公告)号：US09922705B1
公开(公告)日：2018-03-20
申请号：US15621222
申请日：2017-06-13
发明人： Vinh Diep , Xuehong Yu , Zhengyi Zhang , Yingda Dong
CPC分类号： G11C11/5635 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C2216/28
摘要： A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when the voltages of the drain and source ends of a memory string are increased to an erase level which charges up the channel. In one approach, the voltage of the word line which is adjacent to a select gate line is temporarily increased. Another approach builds off the first approach by temporarily increasing the voltage of the select gate line at the same time as the increase in the word line voltage.
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公开(公告)号：US09887002B1
公开(公告)日：2018-02-06
申请号：US15584584
申请日：2017-05-02
发明人： Zhengyi Zhang , Yingda Dong
IPC分类号： G11C7/12 , G11C11/56 , G11C16/16 , G11C16/08 , G11C16/04 , H01L27/1158 , H01L27/1157
CPC分类号： G11C11/5628 , G11C7/12 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/32 , G11C16/3427 , H01L27/11556 , H01L27/11582
摘要： Apparatuses and techniques are described for reducing or eliminating program disturb in non-volatile storage. In one aspect, the ramp rate of a voltage applied to a dummy word line is reduced during programming of edge word lines. In one embodiment, a slower than normal ramp rate is used for a dummy word line when the word line selected for programming is an edge word line, but a normal ramp rate is used for the dummy word line when the word line selected for programming is a middle word line.
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7.发明授权公开(公告)号：US10854300B2
公开(公告)日：2020-12-01
申请号：US16898145
申请日：2020-06-10
发明人： Ching-Huang Lu , Vinh Diep , Zhengyi Zhang
摘要： Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.
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公开(公告)号：US10762973B1
公开(公告)日：2020-09-01
申请号：US16408975
申请日：2019-05-10
发明人： Ching-Huang Lu , Zhengyi Zhang
摘要： Program disturb is suppressed during a program recovery phase of a program operation in a memory device. The duration of the recovery phase can be increased when the risk of program disturb is greater due to factors such as temperature, the position of the selected word line, the number of program-erase cycles and the program pulse magnitude. In other approaches, the risk of program disturb is reduced by providing an early ramp down of the voltages of the drain-side word line relative to a ramp down of the voltages of the source-side word lines, providing an early ramp down of the bit line voltage of the inhibited NAND strings relative to the ramp down of the select gate voltage or setting a lower recovery voltage for the source-side word lines relative to the recovery voltage of the drain-side word lines.
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9.发明申请公开(公告)号：US20190311772A1
公开(公告)日：2019-10-10
申请号：US15948761
申请日：2018-04-09
发明人： Vinh Diep , Ching-Huang Lu , Zhengyi Zhang , Yingda Dong
摘要： Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.
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公开(公告)号：US09786378B1
公开(公告)日：2017-10-10
申请号：US15367549
申请日：2016-12-02
发明人： Zhengyi Zhang , Liang Pang , Caifu Zeng , Xuehong Yu , Yingda Dong
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3445 , G11C16/3477
摘要： A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance.
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