-
公开(公告)号：US10008277B2
公开(公告)日：2018-06-26
申请号：US15262262
申请日：2016-09-12
发明人： Liang Pang , Xuehong Yu , Yingda Dong , Nian Niles Yang
IPC分类号： G11C16/34 , G11C16/28 , G11C16/16 , G11C16/04 , G11C16/10 , G11C16/08 , H01L27/1157 , H01L27/11582
CPC分类号： G11C16/3495 , G11C7/14 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/3445 , G11C16/349 , H01L27/1157 , H01L27/11582
摘要： Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. However, there can be a variation in the endurance of cells even within a single die. By evaluating the dummy memory cells, an early warning can be obtained of a degradation of the data memory cells. Moreover, there is no interference with the operation of the data memory cells. Based on a number of dummy memory cells which have a Vth below a demarcation voltage, a corrective action is taken such as adjusting read voltages, an initial program voltage and/or an initial erase voltage, or marking the block as being bad and recovering the data.
-
公开(公告)号：US20180113759A1
公开(公告)日：2018-04-26
申请号：US15333440
申请日：2016-10-25
发明人： Idan Alrod , Eran Sharon , Alon Eyal , Liang Pang , Evgeny Mekhanik
CPC分类号： G06F11/1068 , G06F11/10 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C29/52 , G11C2207/2281
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
-
3.发明申请公开(公告)号：US20170373086A1
公开(公告)日：2017-12-28
申请号：US15190574
申请日：2016-06-23
发明人： Liang Pang , Jayavel Pachamuthu , Yingda Dong
IPC分类号： H01L27/11582 , H01L27/11568 , H01L21/28 , H01L21/02 , H01L29/66 , H01L21/311
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/02667 , H01L21/28282 , H01L21/31111 , H01L27/11568 , H01L29/42368 , H01L29/66545 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/7926
摘要： Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si3N4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO2. The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO2. The two SiO2 layers together form a blocking oxide layer.
-
公开(公告)号：US10262743B2
公开(公告)日：2019-04-16
申请号：US15440185
申请日：2017-02-23
发明人： Idan Alrod , Eran Sharon , Alon Eyal , Liang Pang , Evgeny Mekhanik
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die.
-
公开(公告)号：US20180203762A1
公开(公告)日：2018-07-19
申请号：US15921165
申请日：2018-03-14
发明人： Idan Alrod , Eran Sharon , Alon Eyal , Liang Pang , Evgeny Mekhanik
CPC分类号： G06F11/1068 , G06F11/08 , G06F11/10 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C29/52 , G11C2207/2281
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
-
公开(公告)号：US10020314B1
公开(公告)日：2018-07-10
申请号：US15448409
申请日：2017-03-02
发明人： Ashish Baraskar , Liang Pang , Yanli Zhang , Ching-Huang Lu , Yingda Dong
IPC分类号： H01L21/336 , H01L27/11519 , H01L27/11565 , H01L27/11524 , H01L27/1157 , H01L27/11556 , H01L27/11582 , H01L21/8234 , H01L27/11526 , H01L27/11573
CPC分类号： H01L27/11519 , H01L21/823412 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.
-
公开(公告)号：US20180122814A1
公开(公告)日：2018-05-03
申请号：US15846620
申请日：2017-12-19
发明人： Ashish Baraskar , Liang Pang , Yanli Zhang , Raghuveer Makala , Yingda Dong
IPC分类号： H01L27/1157 , H01L27/105 , H01L27/11565 , H01L27/11582
CPC分类号： H01L27/1157 , H01L27/1052 , H01L27/11565 , H01L27/11582 , H01L29/7926
摘要： A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.
-
公开(公告)号：US09831118B1
公开(公告)日：2017-11-28
申请号：US15163236
申请日：2016-05-24
发明人： Liang Pang , Yingda Dong , Jayavel Pachamuthu , Ching-Huang Lu
IPC分类号： H01L21/768 , H01L27/115 , H01L23/532 , H01L21/28 , H01L23/528 , H01L23/522 , H01L27/1157 , H01L27/11582
CPC分类号： H01L21/7682 , H01L21/28282 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L27/1157 , H01L27/11582 , H01L29/66833
摘要： Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates.
-
公开(公告)号：US09786378B1
公开(公告)日：2017-10-10
申请号：US15367549
申请日：2016-12-02
发明人： Zhengyi Zhang , Liang Pang , Caifu Zeng , Xuehong Yu , Yingda Dong
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3445 , G11C16/3477
摘要： A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance.
-
公开(公告)号：US09607707B1
公开(公告)日：2017-03-28
申请号：US15198228
申请日：2016-06-30
发明人： Liang Pang , Yingda Dong , Xuehong Yu , Jingjian Ren
CPC分类号： G11C16/26 , G11C7/04 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/3459
摘要： Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. The word line creep up could cause electrons to trap in shallow interface traps of a memory cell, hence impacting its threshold voltage. In one aspect, trapped electrons are removed (e.g., de-trapped) from shallow interface traps of a memory cell using a weak erase operation. Therefore, problems associated with word line voltage creep up are reduced or prevented. Thus, the memory cell can be sensed without waiting, while still providing an accurate result. The weak erase could be part of a sensing operation, but that is not required. For example, the weak erase could be incorporated into the beginning part of a read operation, which provides for a very efficient solution.
-
-
-
-
-
-
-
-
-
搜索结果
38 条记录 (耗时 0.028 秒)
