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    Light emitting device
    21.
    发明授权
    Light emitting device 有权

    公开(公告)号：US10263059B2

    公开(公告)日：2019-04-16

    申请号：US15907334

    申请日：2018-02-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

    IPC: H01L27/32 ,  H01L27/12 ,  H01L29/786

    Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

    LIGHT EMITTING DEVICE
    22.
    发明申请
    LIGHT EMITTING DEVICE 审中-公开

    公开(公告)号：US20180254311A1

    公开(公告)日：2018-09-06

    申请号：US15907334

    申请日：2018-02-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

    IPC: H01L27/32 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

    Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

    Pulse Output Circuit, Shift Register and Display Device
    24.
    发明申请
    Pulse Output Circuit, Shift Register and Display Device 有权
    脉冲输出电路，移位寄存器和显示器件

    公开(公告)号：US20170076820A1

    公开(公告)日：2017-03-16

    申请号：US15343373

    申请日：2016-11-04

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

    IPC: G11C19/28 ,  G09G3/36 ,  H01L27/12

    CPC classification number: G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

    Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

    Abstract translation: 脉冲被输入到TFT 101和104，使得TFT将导通，然后节点α的电位上升。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，TFT 105然后导通，并且输出节点的电位随着时钟信号达到电平H而上升。另一方面，由于电容107的操作，TFT 105的栅电极的电位进一步上升， 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，由TFT 105的阈值引起的电压下降，输出节点的电位上升到VDD。

    LIGHT EMITTING DEVICE
    26.
    发明申请
    LIGHT EMITTING DEVICE 有权
    发光装置

    公开(公告)号：US20150035033A1

    公开(公告)日：2015-02-05

    申请号：US14322990

    申请日：2014-07-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

    IPC: H01L27/32 ,  H01L27/12

    CPC classification number: H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

    Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

    Abstract translation: 提供一种可以防止由于泄漏或其它原因引起的栅极电压变化并且同时可以防止开口率降低的发光器件。 电容器存储器由连接布线，绝缘膜和电容布线形成。 连接布线形成在栅电极和像素的TFT的有源层上，并与有源层连接。 绝缘膜形成在连接布线上。 电容布线形成在绝缘膜上。 这种结构使得电容器存储与TFT重叠，从而在保持开口率降低的同时增加电容器存储的容量。 因此，可以避免由于泄漏或其他原因导致的栅极电压的变化，以防止OLED的亮度变化和模拟驱动中屏幕的闪烁。

    Pulse Output Circuit, Shift Register and Display Device
    27.
    发明申请
    Pulse Output Circuit, Shift Register and Display Device 有权
    脉冲输出电路，移位寄存器和显示器件

    公开(公告)号：US20140327008A1

    公开(公告)日：2014-11-06

    申请号：US14332468

    申请日：2014-07-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

    IPC: H01L27/12 ,  G02F1/1333

    CPC classification number: G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

    Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

    Abstract translation: 脉冲被输入到TFT 101和104，使得TFT将导通，然后节点α的电位上升。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，TFT 105然后导通，并且输出节点的电位随着时钟信号达到电平H而上升。另一方面，由于电容107的操作，TFT 105的栅电极的电位进一步上升， 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，由TFT 105的阈值引起的电压下降，输出节点的电位上升到VDD。

    LIGHT EMITTING DEVICE
    28.
    发明申请
    LIGHT EMITTING DEVICE 有权
    发光装置

    公开(公告)号：US20140021459A1

    公开(公告)日：2014-01-23

    申请号：US14037437

    申请日：2013-09-26

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

    IPC: H01L27/32

    CPC classification number: H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

    Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

    Abstract translation: 提供一种可以防止由于泄漏或其它原因引起的栅极电压变化并且同时可以防止开口率降低的发光器件。 电容器存储器由连接布线，绝缘膜和电容布线形成。 连接布线形成在栅电极和像素的TFT的有源层上，并与有源层连接。 绝缘膜形成在连接布线上。 电容布线形成在绝缘膜上。 这种结构使得电容器存储与TFT重叠，从而在保持开口率降低的同时增加电容器存储的容量。 因此，可以避免由于泄漏或其他原因导致的栅极电压的变化，以防止OLED的亮度变化和模拟驱动中屏幕的闪烁。

    Pulse output circuit, shift register, and display device
    30.
    发明授权
    Pulse output circuit, shift register, and display device 有权

    公开(公告)号：US10304399B2

    公开(公告)日：2019-05-28

    申请号：US15447232

    申请日：2017-03-02

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

    IPC: G09G3/36 ,  G11C19/28

    Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

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