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公开(公告)号:US08340092B2
公开(公告)日:2012-12-25
申请号:US11831073
申请日:2007-07-31
申请人: Teruo Kaganoi , Takeshi Aimoto
发明人: Teruo Kaganoi , Takeshi Aimoto
IPC分类号: H04L12/28
CPC分类号: H04L49/555 , H04L49/3009 , H04L49/351 , H04L49/354 , H04L49/557
摘要: A switching system includes a data collection device, one or more switching devices. The data collection device is for collection of first data subject to specific processing. The switching devices directly or indirectly connected to the data collection device. At least one of the switching devices includes a determination module that determines whether received data is the first data or is second data which is not subject to the specific processing, and a marking module that puts first marking on the received data determined to be the first data. The switching devices respectively includes a transferring processor that executes a first transfer process for sending the received data to the data collection device when the received data has the first marking, and a second transfer process that sends the received data to the specified destination when the received data does not have the first marking.
摘要翻译: 切换系统包括数据收集装置,一个或多个切换装置。 数据采集装置用于收集经受特定处理的第一数据。 交换设备直接或间接连接到数据采集设备。 至少一个切换装置包括:确定模块,其确定所接收的数据是否是第一数据,也可以是不受特定处理的第二数据;以及标记模块,其将接收到的数据确定为第一标记 数据。 交换设备分别包括传送处理器,当接收到的数据具有第一标记时,执行用于将接收到的数据发送到数据收集设备的第一传送处理;以及第二传送处理,当接收到的数据被接收时,将接收的数据发送到指定的目的地 数据没有第一个标记。
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公开(公告)号:US07095742B2
公开(公告)日:2006-08-22
申请号:US10091392
申请日:2002-03-07
申请人: Teruo Kaganoi , Dai Shizume , Yasuyuki Ikegai
发明人: Teruo Kaganoi , Dai Shizume , Yasuyuki Ikegai
CPC分类号: H04L45/00 , H04L45/7453
摘要: A packet receiving circuit splits the packet received from a transmission channel into a fixed length of cells and outputs the cells, a search key extracting circuit extracts a predetermined search key from the above-mentioned cells, a CAM performs retrieval based on the above-mentioned search key and outputs a memory address corresponding to the search key, a matching entry address receiving and associative data address transmitting circuit calculates the memory address of an associative data memory based on the above-mentioned memory address and outputs the information stored in the associative data memory as associative data, a search result (associative data) receiving circuit receives the above-mentioned associative data and performs header updating and destination address of the above-mentioned cells, and a packet transmitting circuit outputs the above-mentioned cells in the form of a packet to a transmission channel.
摘要翻译: 分组接收电路将从传输信道接收的分组分离成小区的固定长度并输出小区,搜索关键字提取电路从上述小区中提取预定的搜索关键字,CAM根据上述提到的检索键 搜索键并输出与搜索关键字对应的存储器地址,匹配的入口地址接收和关联数据地址发送电路基于上述存储器地址来计算关联数据存储器的存储器地址,并输出存储在关联数据中的信息 存储器作为关联数据,搜索结果(关联数据)接收电路接收上述关联数据并执行上述单元的标题更新和目的地地址,并且分组发送电路输出上述单元格的形式 到传输信道的分组。
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公开(公告)号:US06772269B1
公开(公告)日:2004-08-03
申请号:US09704628
申请日:2000-11-02
申请人: Teruo Kaganoi
发明人: Teruo Kaganoi
IPC分类号: G06F1336
CPC分类号: G06F13/4059
摘要: A bus switch system having an adapter, a first input and first output register in cascade connection on a data transferring bus of bus switch that comprise input and output shift registers. There is also a bridge, the second input and second output registers are in a cascade connection on the first data transferring bus form a shift register. This allows data to be transferred to an adjacent adapter at one clock cycle, thereby the data transfer is made faster. The data transfer on the first and second data transferring buses is conducted in one direction and input/output control is optimally conducted by first and second control means so that switch control in data transfer is made easier.
摘要翻译: 一种总线开关系统,其具有适配器,第一输入和第一输出寄存器,其级联连接在总线开关的数据传输总线上,其包括输入和输出移位寄存器。 还有一个桥,第二个输入和第二个输出寄存器在第一个数据传输总线上形成一个移位寄存器的级联连接。 这允许以一个时钟周期将数据传送到相邻的适配器,从而使数据传输更快。 第一和第二数据传送总线上的数据传输在一个方向上进行,并且由第一和第二控制装置最佳地进行输入/输出控制,使得数据传送中的开关控制变得更容易。
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公开(公告)号:US06614676B2
公开(公告)日:2003-09-02
申请号:US10245277
申请日:2002-09-18
申请人: Teruo Kaganoi
发明人: Teruo Kaganoi
IPC分类号: G11C1500
CPC分类号: G11C15/00
摘要: A content-addressable memory device with multiple WORD lines has: a first memory block to store whether there is a hit during current time period; a second memory block to store whether there is a hit during a period preceding the current time period, the first and second memory blocks being provided for each WORD line; and elements for selecting a WORD line to determine a WORD line to be aged out according to values stored in the first and second memory blocks.
摘要翻译: 具有多个WORD线的可内容寻址的存储器件具有:存储当前时间段内是否存在命中的第一存储器块; 第二存储块,用于存储在当前时间段之前的时段期间是否有命中,为每个WORD行提供第一和第二存储器块; 以及用于选择WORD行以根据存储在第一和第二存储器块中的值来确定要老化的WORD行的元素。
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公开(公告)号:US5953315A
公开(公告)日:1999-09-14
申请号:US748515
申请日:1996-11-08
申请人: Teruo Kaganoi
发明人: Teruo Kaganoi
IPC分类号: H04Q3/00 , G11C15/04 , H04L12/815 , H04L12/863 , H04Q11/04 , H04L12/56
CPC分类号: H04Q11/0478 , H04L2012/5679 , H04L2012/5681
摘要: An ATM cell sending system includes a first memory, a second memory, a retrieval circuit, and a memory control circuit. The first memory temporarily stores an input cell, outputs a cell storage address, and, in response to input of the cell storage address, outputs the cell stored at the input cell storage address. The second memory stores the cell storage address from the first memory and outputs the readout cell storage address to the first memory. The retrieval circuit uses an address corresponding to a reservation time for cell sending as a start address to retrieve a first free address after the reservation time from the second memory. The memory control circuit writes the cell storage address of the first memory at the free address of the second memory, which is retrieved by the retrieval circuit, and reads out the cell storage address of the first memory from an address of the second memory which corresponds to a current time.
摘要翻译: ATM信元发送系统包括第一存储器,第二存储器,检索电路和存储器控制电路。 第一存储器临时存储输入单元,输出单元存储地址,并且响应于单元存储地址的输入,输出存储在输入单元存储地址处的单元。 第二存储器存储来自第一存储器的单元存储地址,并将读出单元存储地址输出到第一存储器。 检索电路使用与小时发送的预约时间相对应的地址作为起始地址,从第二存储器取出预约时间之后的第一空闲地址。 存储器控制电路将第一存储器的单元存储地址写入由检索电路检索的第二存储器的空闲地址,并从对应的第二存储器的地址读出第一存储器的单元存储地址 到当前时间
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公开(公告)号:US09596191B2
公开(公告)日:2017-03-14
申请号:US13991281
申请日:2012-01-19
IPC分类号: H04L12/933 , H04L12/703
CPC分类号: H04L49/15 , H04L41/0672 , H04L43/08 , H04L45/28 , H04L69/40
摘要: A network relay system includes a plurality of communication devices. Each of the communication devices includes a data plane that transfers an input packet according to routing information, and a control plane having a processing unit that learns the routing information, and a control system repeater. The data planes of the respective communication devices can realize a non-blocking communication therebetween. Also, the control system repeater of an operational system receives the routing information from the processing unit, sets the routing information for the data plane of the subject communication device, and transmits the routing information to the control system repeater of the other communication device. The control system repeater of a standby system receives the routing information, and sets the routing information for the data plane of the subject communication device.
摘要翻译: 网络中继系统包括多个通信设备。 每个通信设备包括根据路由信息传送输入分组的数据平面和具有学习路由信息的处理单元的控制平面以及控制系统中继器。 各个通信设备的数据平面可以实现它们之间的非阻塞通信。 此外,操作系统的控制系统中继器从处理单元接收路由信息,设置对象通信设备的数据平面的路由信息,并将路由信息发送到另一通信设备的控制系统中继器。 备用系统的控制系统中继器接收路由信息,并设置对象通信设备的数据平面的路由信息。
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公开(公告)号:US09240894B2
公开(公告)日:2016-01-19
申请号:US13871035
申请日:2013-04-26
申请人: Teruo Kaganoi , Naoya Kumita
发明人: Teruo Kaganoi , Naoya Kumita
CPC分类号: H04L12/185 , H04L12/462 , H04L12/4625 , H04L12/4633 , H04L12/4641
摘要: A network system includes: a core switch; and an edge switch. The edge switch includes: a join message identification unit; and a marking unit. The join message identification unit identifies a join message from among MAC frames from the user network. The marking unit marks mark information to a header of a MAC-in-MAC frame in which the identified join message is encapsulated. The core switch includes: a plurality of input/output ports; a mark identification unit; and a port setup unit. The mark identification unit identifies a MAC-in-MAC frame to whose a header the mark information is marked. The port setup unit associates a multicast group of a join message which is encapsulated in the identified MAC-in-MAC frame, with an input/output port to which the identified MAC-in-MAC frame is input.
摘要翻译: 网络系统包括:核心交换机; 和边缘开关。 边缘切换器包括:加入消息识别单元; 和标记单元。 加入消息识别单元从来自用户网络的MAC帧中识别加入消息。 标记单元将标记信息标记到MAC-in-MAC帧的标题中,其中标识的加入消息被封装在其中。 核心交换机包括:多个输入/输出端口; 标记识别单元; 和端口设置单元。 标记识别单元标识标记信息被标记的标题的MAC-in-MAC帧。 端口设置单元将封装在所识别的MAC-in-MAC帧中的加入消息的多播组与所输入的MAC-in-MAC帧的输入/输出端口相关联。
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公开(公告)号:US20080123622A1
公开(公告)日:2008-05-29
申请号:US11831073
申请日:2007-07-31
申请人: Teruo Kaganoi , Takeshi Aimoto
发明人: Teruo Kaganoi , Takeshi Aimoto
IPC分类号: H04L12/28
CPC分类号: H04L49/555 , H04L49/3009 , H04L49/351 , H04L49/354 , H04L49/557
摘要: A switching system includes a data collection device, one or more switching devices. The data collection device is for collection of first data subject to specific processing. The switching devices directly or indirectly connected to the data collection device. At least one of the switching devices includes a determination module that determines whether received data is the first data or is second data which is not subject to the specific processing, and a marking module that puts first marking on the received data determined to be the first data. The switching devices respectively includes a transferring processor that executes a first transfer process for sending the received data to the data collection device when the received data has the first marking, and a second transfer process that sends the received data to the specified destination when the received data does not have the first marking.
摘要翻译: 切换系统包括数据收集装置,一个或多个切换装置。 数据采集装置用于收集经受特定处理的第一数据。 交换设备直接或间接连接到数据采集设备。 至少一个切换装置包括:确定模块,其确定所接收的数据是否是第一数据,也可以是不受特定处理的第二数据;以及标记模块,其将接收到的数据确定为第一标记 数据。 交换设备分别包括传送处理器,当接收到的数据具有第一标记时,执行用于将接收到的数据发送到数据收集设备的第一传送处理;以及第二传送处理,当接收到的数据被接收时,将接收的数据发送到指定的目的地 数据没有第一个标记。
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29.
公开(公告)号:US5854783A
公开(公告)日:1998-12-29
申请号:US674759
申请日:1996-07-02
申请人: Teruo Kaganoi
发明人: Teruo Kaganoi
IPC分类号: H04Q3/00 , G11C15/04 , H04L12/70 , H04L12/801 , H04L12/811 , H04L12/911 , H04Q11/04 , H04J3/14 , H04L12/56
CPC分类号: H04L12/5602 , H04Q11/0478 , H04L2012/5636
摘要: A cell interval determination apparatus for usage parameter control, includes a counter, a memory, a cell arrival interval check unit, and a control unit. The counter is incremented every time a cell has arrived in an asynchronous mode to represent a cell arrival time. The memory stores, in units of cell type information, cell information consisting of cell type information included in the cell, the cell arrival time counted by the counter, a cell arrival interval defined value which is set in units of cell type information, and flag information representing a retrieval target/non-retrieval target. The cell arrival interval check unit calculates a time difference between the cell arrival time stored in the memory and the cell arrival time represented by the counter and determines a cell which violates the cell arrival interval defined value stored in the memory. The control unit retrieves, from the memory in accordance with the flag information, cell information having the same cell type information as that extracted from the arriving cell, designates to start the cell arrival interval check unit in accordance with a retrieval result, and stores the cell information associated with the arriving cell in the memory in accordance with the retrieval result and a determination result of the cell arrival interval check unit.
摘要翻译: 一种用于使用参数控制的信元间隔确定装置,包括计数器,存储器,单元到达间隔检查单元和控制单元。 每当一个单元到达异步模式以计算单元到达时间时,计数器递增。 存储器以单元类型信息为单位存储由单元格中包含的单元类型信息组成的单元信息,由计数器计数的单元到达时间,以单元类型信息为单位设置的单元到达间隔定义值,以及标志 表示检索对象/非检索对象的信息。 单元到达间隔检查单元计算存储在存储器中的单元到达时间与由计数器表示的单元到达时间之间的时间差,并且确定违反存储在存储器中的单元到达间隔定义值的单元。 控制单元根据标志信息从存储器检索具有与从到达小区提取的单元类型信息相同的单元类型信息的单元信息,根据检索结果指定启动单元到达间隔检查单元,并存储 根据检索结果与存储器中的到达单元相关联的单元信息以及单元到达间隔检查单元的确定结果。
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30.
公开(公告)号:US09019842B2
公开(公告)日:2015-04-28
申请号:US13403461
申请日:2012-02-23
申请人: Shinich Akahane , Teruo Kaganoi
发明人: Shinich Akahane , Teruo Kaganoi
IPC分类号: H04L12/703 , H04L12/26
CPC分类号: H04L43/10 , H04L43/026
摘要: A relay device comprises: a packet type determining unit that determines: whether a received packet is a monitoring packet, sent by a first communication device that monitors a network connection state, set the first communication device as the sending source, and set a second communication device that is monitored as the sending destination; and whether the received packet is a monitoring response packet sent as the response to the monitoring packet with sending source address and destination address of monitoring packet interchanged; a transfer processing unit that receives the monitoring packet and transfers it to a destination; a monitoring unit that monitors receipt of the monitoring response packet within a specified period; and a failure notification packet sending unit that generates a failure notification packet and sends it to a specified destination, when the monitoring response packet is not received within the specified period.
摘要翻译: 中继装置包括:分组类型确定单元,确定接收到的分组是否是由监视网络连接状态的第一通信设备发送的监视分组,将第一通信设备设置为发送源,并设置第二通信 监控作为发送目的地的设备; 接收到的分组是否是作为对监视分组的响应而发送的监视响应分组,其中发送源地址和监视分组的目的地地址互换; 传送处理单元,接收监视包并将其传送到目的地; 监视单元,监视在指定时间段内的监视响应分组的接收; 以及故障通知分组发送单元,当在规定的时间段内未接收到所述监视响应分组时,生成故障通知分组并将其发送到指定的目的地。
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