公开(公告)号：US20120125679A1

公开(公告)日：2012-05-24

申请号：US13032653

申请日：2011-02-23

Applicant: YUNG-CHIEH CHEN ,  CHENG-HSIEN LEE ,  PO-CHUAN HSIEH ,  SHOU-KUO HSU ,  SHIN-TING YEN

Inventor： YUNG-CHIEH CHEN ,  CHENG-HSIEN LEE ,  PO-CHUAN HSIEH ,  SHOU-KUO HSU ,  SHIN-TING YEN

IPC: H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K1/116

Abstract: A printed circuit board includes an insulating board, a pair of differential vias, and a number of wiring layers. A pair of via holes extends through opposite surfaces of the insulating board. The differential vias correspond to the pair of via holes. Each differential via includes a metal plated barrel and two via capture pads. The plated barrel is plated on the inner surface of the respective via hole, and terminates at each of the two opposite surfaces of the insulating board. The via capture pads are formed on the opposite surfaces of the insulating board around the openings of the via hole, and are electrically connected to the plated barrel. The wiring layers are arranged in the insulating board, and each define a clearance hole surrounding all of the via capture pads.

Abstract translation: 印刷电路板包括绝缘板，一对差动通孔和多个布线层。 一对通孔延伸穿过绝缘板的相对表面。 差分过孔对应于一对通孔。 每个差分通孔包括一个金属电镀桶和两个通孔捕获垫。 电镀桶被镀在相应通孔的内表面上，并且终止于绝缘板的两个相对表面的每一个。 通孔捕获垫形成在绝缘板的围绕通孔的开口的相对表面上，并且电连接到电镀桶。 布线层布置在绝缘板中，并且每个限定围绕所有通孔捕获垫的间隙孔。

公开(公告)号：US20110301922A1

公开(公告)日：2011-12-08

申请号：US12958397

申请日：2010-12-02

Applicant: WEN-LAING TSENG ,  CHENG-HSIEN LEE ,  SHEN-CHUN LI ,  YU-CHANG PAI ,  SHOU-KUO HSU

Inventor： WEN-LAING TSENG ,  CHENG-HSIEN LEE ,  SHEN-CHUN LI ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC: G06F17/50 ,  G06F17/10

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: A simulation system for producing equivalent circuits reads data corresponding to a tabular W element format in a storage device, and adds data of the tabular W element format file using interpolation algorithm. A frequency-dependent transmission matrix is transformed into an N-port network matrix describing electrical properties of a multi-input and multi-output network. An N-port network matrix is transformed into a S-parameter matrix. A range of frequency of a s-parameter is determined and numbers of pole-residue, times for recursion and durable maximum system errors in the equivalent circuit is also determined. A a vector fitting algorithm is performed and a rational function matrix composed with s-parameters is produced, to produce a general SPICE equivalent circuit based on the generated rational function matrix.

Abstract translation: 用于产生等效电路的仿真系统在存储装置中读取对应于表格W元素格式的数据，并且使用插值算法来添加表格W元素格式文件的数据。 频率依赖传输矩阵被转换成描述多输入和多输出网络的电特性的N端口网络矩阵。 将N端口网络矩阵转换为S参数矩阵。 确定s参数的频率范围，并确定等效电路中极点残差，递归次数和持久最大系统误差的数量。 执行向量拟合算法，并产生由s参数组成的有理函数矩阵，以产生基于生成的有理函数矩阵的一般SPICE等效电路。

公开(公告)号：US20110231175A1

公开(公告)日：2011-09-22

申请号：US12978417

申请日：2010-12-24

Applicant: CHENG-HSIEN LEE ,  SHOU-KUO HSU

Inventor： CHENG-HSIEN LEE ,  SHOU-KUO HSU

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: In an electronic device and a method of generating composite electrical signals, a plurality of post-processing software is installed. An output file, which comprises times and voltages of data points that represent an electrical signal, of an electronic circuit simulation software is loaded, and is read using the installed post-processing software. A time interval of outputs of the electrical signal is obtained by selecting an output type of the electrical signal. The worst bit combination of outputs of the electrical signal is analyzed according to the times, the voltage, and the time interval, and a composite electrical signal is generated according to the worst bit combination.

Abstract translation: 在电子设备和产生复合电信号的方法中，安装了多个后处理软件。 加载电子电路仿真软件的包括代表电信号的数据点的时间和电压的输出文件，并使用安装的后处理软件进行读取。 通过选择电信号的输出类型来获得电信号的输出的时间间隔。 根据时间，电压和时间间隔分析电信号输出的最差位组合，并根据最差位组合生成复合电信号。

公开(公告)号：US20110066764A1

公开(公告)日：2011-03-17

申请号：US12606120

申请日：2009-10-26

Applicant: SHOU-KUO HSU ,  CHENG-HSIEN LEE

Inventor： SHOU-KUO HSU ,  CHENG-HSIEN LEE

IPC: G06F3/00

CPC classification number: G06F13/4282

Abstract: A system for selecting high speed serial signals includes a loading module, a layout selecting module, a data processing module, and an output module. The loading module reads a chip package length file; a layout selecting module reads a layout file and selects high speed serial signals preset by a user; the data processing module selects pins information of a start chip and a terminal chip transmit the selected high speed serial signals and finds the chip package length information, and analyzes interrupt points of the layout character from the start chip and outputs the chip package length information of the start chip, the layout length information, and the chip package length information of the terminal chip in sequence to the output module, to convert into a table and displays the table via a display device.

Abstract translation: 用于选择高速串行信号的系统包括加载模块，布局选择模块，数据处理模块和输出模块。 加载模块读取芯片封装长度文件; 布局选择模块读取布局文件并选择用户预设的高速串行信号; 数据处理模块选择起始芯片的引脚信息和终端芯片发送所选择的高速串行信号，并找到芯片封装长度信息，并从启动芯片分析布局字符的中断点，并输出芯片封装长度信息 开始芯片，布局长度信息，以及终端芯片的芯片封装长度信息顺序地输出到输出模块，转换成表格并通过显示装置显示表格。

公开(公告)号：US20130254729A1

公开(公告)日：2013-09-26

申请号：US13585855

申请日：2012-08-15

Applicant: YA-LING HUANG ,  CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： YA-LING HUANG ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/82

Abstract: A device and a method reads a circuit printed circuit (PCB) layout file, extracts arrangement information of all the interference source components and signal transmission lines of the PCB layout file, and selects a interference source component from the PCB layout file, then determines if there is any signal transmission line is laid under the selected interference source component.

Abstract translation: 一种设备和方法读取电路印刷电路（PCB）布局文件，提取PCB布局文件的所有干扰源组件和信号传输线的布置信息，并从PCB布局文件中选择干扰源组件，然后确定是否 在所选择的干扰源组件下面有任何信号传输线。

公开(公告)号：US20130158925A1

公开(公告)日：2013-06-20

申请号：US13585856

申请日：2012-08-15

Applicant: YA-LING HUANG ,  CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： YA-LING HUANG ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: G06F19/00 ,  G01N37/00

CPC classification number: G06F17/5081

Abstract: A computer-based method and a computing device for checking differential pairs of a printed circuit board layout are provided. The computing device determines the via pitch between switching vias of a differential pair according to the coordinates of the centers of the switching vias, determines the via gap between the switching vias of adjacent two differential pairs according to the radius and the coordinates of the centers of the switching vias, and determines that the switching vias does not satisfy design standards if the via pitch does not fall in an input via pitch range, or the via gap does not fall in an input via gap range.

Abstract translation: 提供了一种用于检查印刷电路板布局的差分对的基于计算机的方法和计算装置。 计算装置根据切换通孔的中心坐标来确定差分对的切换通孔之间的经过间距，根据半径的中心确定相邻两个差分对的切换通孔之间的通孔间隙 并且如果通孔间距没有通过间距范围落入输入，或者通孔间隙不通过间隙范围落入输入，则确定开关通孔不满足设计标准。

公开(公告)号：US20120304145A1

公开(公告)日：2012-11-29

申请号：US13434858

申请日：2012-03-30

Applicant: YUNG-CHIEH CHEN ,  SHOU-KUO HSU ,  SHIN-TING YEN

Inventor： YUNG-CHIEH CHEN ,  SHOU-KUO HSU ,  SHIN-TING YEN

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: An electronic device includes a wiring unit. The wiring unit creates one or more circuit diagrams for a design of a first circuit board, and setting electrical rules for components of the first circuit board in each of the one or more diagrams. Based on the one or more diagrams having the electrical rules, the wiring unit generates a wiring diagram for the design of the first circuit board by executing a wiring application. If a second circuit board desires to use a circuit diagram of the first circuit board, the wiring unit copies the circuit diagram having the electrical rules into the wiring application. Then, based on the copied circuit diagram having the electrical rules and particular circuit diagrams of the second circuit board, and the wiring unit creates a wiring diagram for the design of the second circuit board by executing the wiring application.

Abstract translation: 电子设备包括接线单元。 接线单元为第一电路板的设计创建一个或多个电路图，并且在一个或多个图中的每一个中为第一电路板的部件设置电气规则。 基于具有电气规则的一个或多个图，布线单元通过执行布线应用产生用于设计第一电路板的布线图。 如果第二电路板希望使用第一电路板的电路图，则布线单元将具有电气规则的电路图复制到布线应用中。 然后，基于具有电气规则的复制电路图和第二电路板的具体电路图，并且布线单元通过执行布线应用来创建用于第二电路板的设计的布线图。

公开(公告)号：US20120273254A1

公开(公告)日：2012-11-01

申请号：US13217626

申请日：2011-08-25

Applicant: HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: H01B5/00

CPC classification number: H05K1/111 ,  H05K1/0242 ,  H05K1/025 ,  H05K2201/09736 ,  Y02P70/611

Abstract: A pad includes a first mating section and a second mating section. The first mating section includes a first horizontal plane and a first inclined plane. The second mating section includes a second horizontal plane and a second inclined plane. The first mating section is a copper foil capable of being connected to a wire. The second mating section is made of insulating material. The first inclined plane and the second inclined plane are bonded together.

Abstract translation: 垫包括第一配合部分和第二配合部分。 第一配合部分包括第一水平面和第一倾斜平面。 第二配合部分包括第二水平面和第二倾斜平面。 第一配合部分是能够连接到电线的铜箔。 第二配合部分由绝缘材料制成。 第一倾斜平面和第二倾斜平面结合在一起。

公开(公告)号：US20120269471A1

公开(公告)日：2012-10-25

申请号：US13182428

申请日：2011-07-13

Applicant: SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  SHOU-KUO HSU

Inventor： SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  SHOU-KUO HSU

IPC: F16C17/26

CPC classification number: F16C29/005 ,  B61B3/00 ,  F16C2322/59

Abstract: An exemplary guideway mechanism includes two branches, a group of connecting blocks, and a supporting bracket. The group of connecting blocks includes four connecting blocks arranged at four corners of an imaginary square and connecting the supporting bracket. Each branch includes two parallel rails. Adjacent ends of the rails of each branch respectively connect two adjacent connecting blocks.

Abstract translation: 示例性导轨机构包括两个分支，一组连接块和支撑托架。 该组连接块包括布置在假想方形的四个角处并连接支撑托架的四个连接块。 每个分支包括两个平行导轨。 每个分支的轨道的相邻端分别连接两个相邻的连接块。

公开(公告)号：US20120268283A1

公开(公告)日：2012-10-25

申请号：US13167719

申请日：2011-06-24

Applicant: SHOU-KUO HSU ,  YUNG-CHIEH CHEN ,  HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  WEN-LAING TSENG ,  CHIA-NAN PAI

Inventor： SHOU-KUO HSU ,  YUNG-CHIEH CHEN ,  HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  WEN-LAING TSENG ,  CHIA-NAN PAI

IPC: G08B21/00 ,  G01R17/02

CPC classification number: H05K1/0201 ,  G01R31/043 ,  H05K1/0263 ,  H05K1/029 ,  H05K2201/0979 ,  H05K2201/10212

Abstract: A circuit board includes a current balancing unit that receives a number of current values from ammeters. A minimum current value between the current values is determined by the current balancing unit. Resistance of one or more variable resistors of the current balancing unit is adjusted by the current balancing unit to make the current value from one or more the ammeters serially connected to the one or more the variable resistors to be substantially equal to the minimum current value.

Abstract translation: 电路板包括从电流表接收多个电流值的电流平衡单元。 当前值之间的最小电流值由电流平衡单元确定。 通过电流平衡单元调整电流平衡单元的一个或多个可变电阻器的电阻，使来自一个或多个串联连接到一个或多个可变电阻器的电流器的电流值基本上等于最小电流值。