公开(公告)号：US20160254037A1

公开(公告)日：2016-09-01

申请号：US15148506

申请日：2016-05-06

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C7/12 ,  G11C29/12 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1084 ,  G11C11/401 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C2207/105 ,  G11C2207/2254

Abstract: A semiconductor device may include: a plurality of data pads; a plurality of data buffers each suitable for buffering a signal inputted through a first input node using a voltage inputted through a second input node, and outputting the buffered signal; and a calibration control unit suitable for generating a test signal in a calibration mode, adjusting the level of the test signal, receiving outputs of the plurality of data buffers while adjusting the level of the test signal, and adjusting offsets of the data buffers such that the logical values of the outputs of the data buffers transit when the test signal has a target level.

公开(公告)号：US20160162300A1

公开(公告)日：2016-06-09

申请号：US14686467

申请日：2015-04-14

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G06F9/44 ,  G06F1/26

CPC classification number: G06F9/4403 ,  G06F11/00 ,  G11C5/005

Abstract: A semiconductor device includes an internal signal processing block suitable for generating an internal enable signal and an internal control signal that correspond to an external enable signal and an external control signal, and a monitoring unit suitable for outputting a monitoring signal that corresponds to a predetermined internal signal, based on the internal enable signal and the internal control signal, in an initial operation period.

Abstract translation: 半导体器件包括内部信号处理块，其适用于产生对应于外部使能信号和外部控制信号的内部使能信号和内部控制信号，以及监视单元，适于输出对应于预定内部的监视信号 信号，基于内部使能信号和内部控制信号。

公开(公告)号：US20160035410A1

公开(公告)日：2016-02-04

申请号：US14883305

申请日：2015-10-14

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4087 ,  G11C29/783

Abstract: A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to select one or more bit lines among a plurality of bit lines based on repair information, a second cell array including a plurality of second memory cells connected to the plurality of word lines and the plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected and an activation number update unit configured to update a value stored in the second memory cells, which are connected to the one or more selected bit lines and the activated word line among the plurality of word lines.

Abstract translation: 存储器包括：第一单元阵列，包括连接到多个字线的多个第一存储器单元;位线选择单元，被配置为基于修复信息选择多个位线中的一个或多个位线;第二单元阵列 包括连接到所述多个字线和所述多个位线的多个第二存储器单元，其中连接到对应字线的所述多个第二存储器单元的一组存储当所述一行中相应字线的激活次数时 选择多个连接的位线，激活号码更新单元被配置为更新存储在第二存储器单元中的值，所述值连接到所述多个字线中的一个或多个所选择的位线和激活的字线。

公开(公告)号：US20150348650A1

公开(公告)日：2015-12-03

申请号：US14489020

申请日：2014-09-17

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C29/44 ,  G11C7/20 ,  G11C7/22

CPC classification number: G11C29/44 ,  G11C29/46 ,  G11C2029/0409

Abstract: A semiconductor system includes: a memory controller; and a memory which determines whether to enable a control signal in response to block mode entry signals applied from the memory controller, enters a repair mode in response to a first address and a first command applied from the memory controller, and blocks an entry to the repair mode during an enabling section of the control signal.

Abstract translation: 半导体系统包括：存储器控制器; 以及存储器，其响应于从存储器控制器施加的块模式入口信号来确定是否启用控制信号，响应于从存储器控制器施加的第一地址和第一命令而进入修复模式，并且阻塞到存储器控制器的条目 在控制信号的使能部分期间的修复模式。

公开(公告)号：US20150235694A1

公开(公告)日：2015-08-20

申请号：US14469072

申请日：2014-08-26

Applicant: SK hynix Inc.

Inventor： Chang-Hyun KIM ,  Choung-Ki SONG

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C7/02 ,  G11C11/40615

Abstract: A semiconductor memory device includes a control signal generator suitable for generating a control signal corresponding to temperature information, a refresh controller suitable for enabling a refresh signal for a smart refresh operation at a predetermined moment in response to a refresh command signal and enabling the refresh signal for a normal refresh operation at a moment corresponding to the control signal in response to the refresh command signal, and a data storage suitable for storing a data and performing the smart refresh operation and the normal refresh operation in response to the refresh signal of the refresh controller.

Abstract translation: 半导体存储器件包括适于产生对应于温度信息的控制信号的控制信号发生器，适于在预定时刻响应于刷新命令信号启用用于智能刷新操作的刷新信号的刷新控制器，并使能刷新信号 用于响应于刷新命令信号在对应于控制信号的时刻进行正常的刷新操作，以及适于存储数据并响应于刷新刷新信号执行智能刷新操作和正常刷新操作的数据存储 控制器。

公开(公告)号：US20150221360A1

公开(公告)日：2015-08-06

申请号：US14689994

申请日：2015-04-17

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/406

CPC classification number: G11C11/40607 ,  G11C11/402 ,  G11C11/40611 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

Abstract: A semiconductor memory device includes a memory cell array configured to include a plurality of word lines, a dock enable buffer configured to receive a clock enable signal, a plurality of command buffers configured to receive a plurality of commands, a refresh control unit configured to sequentially activate the plurality of word lines in a self-refresh mode, a command decoder configured to decode the clock enable signal and the plurality of commands, and to allow the refresh control unit to enter the self-refresh mode or exit from the self-refresh mode, and a buffer control unit configured to disable the plurality of command buffers when the clock enable signal is deactivated, and to enable the plurality of command buffers when the refresh control unit exits from the self-refresh mode.

Abstract translation: 一种半导体存储器件，包括配置为包括多条字线的存储单元阵列，配置成接收时钟使能信号的基站使能缓冲器，配置为接收多个命令的多个命令缓冲器，配置为顺序地配置的刷新控制单元 在自刷新模式下激活多个字线，命令解码器，被配置为对时钟使能信号和多个命令进行解码，并允许刷新控制单元进入自刷新模式或退出自刷新 模式，以及缓冲器控制单元，被配置为当所述时钟使能信号被去激活时禁用所述多个命令缓冲器，并且当所述刷新控制单元退出所述自刷新模式时启用所述多个命令缓冲器。

公开(公告)号：US20150049566A1

公开(公告)日：2015-02-19

申请号：US14109237

申请日：2013-12-17

Applicant: SK hynix Inc.

Inventor： Doo-Chan LEE ,  Choung-Ki SONG

IPC: G11C7/04

CPC classification number: G11C7/02 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/408

Abstract: A memory including a first cell block comprising a plurality of first word line groups, and one or more first redundancy word line groups each corresponding to one hit signal of a plurality of hit signals; a second cell block comprising a plurality of second word line groups, and one or more second redundancy word line groups each corresponding to one hit signal of the plurality of hit signals; and a control unit suitable for selecting a cell block and a word line in response to a first input address and refreshing a selected word line based on an input address inputted after the first input address, while refreshing one or more adjacent word lines adjacent to a first selected word line, which is selected by the first input address, in response to the first input address and the hit signals when the first selected word line is adjacent to a redundancy word line, wherein the first input address is first inputted in a target refresh section.

Abstract translation: 一种存储器，包括包括多个第一字线组的第一单元块，以及每个对应于多个命中信号的一个命中信号的一个或多个第一冗余字线组; 包括多个第二字线组的第二单元块以及每个对应于所述多个命中信号的一个命中信号的一个或多个第二冗余字线组; 以及控制单元，其适于响应于第一输入地址选择单元块和字线，并且基于在所述第一输入地址之后输入的输入地址来刷新所选择的字线，同时刷新与所述第一输入地址相邻的一个或多个相邻字线 第一选择字线，其由第一输入地址选择，响应于第一选择字线与冗余字线相邻时的第一输入地址和命中信号，其中第一输入地址首先输入到目标 刷新部分。

公开(公告)号：US20140359208A1

公开(公告)日：2014-12-04

申请号：US14084243

申请日：2013-11-19

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C7/02

Abstract: A memory includes a plurality of word lines each of which are connected to one or more memory cells, an address detection unit suitable for detecting a target address of a target word line among the plurality of word lines, wherein the target word line has an activation history satisfying a predetermined condition, and a control unit suitable for activating one or more word line among the plurality of word lines each time a refresh command is applied, and activating one or more adjacent word lines in response to a refresh command after detection of the target address, wherein the adjacent word line is adjacent to the target word line and identified by the target address.

Abstract translation: 存储器包括多个字线，每个字线连接到一个或多个存储器单元，地址检测单元，适于检测多个字线中的目标字线的目标地址，其中目标字线具有激活 满足预定条件的历史，以及适用于每次施加刷新命令时激活多个字线中的一个或多个字线的控制单元，以及在检测到刷新命令之后响应于刷新命令激活一个或多个相邻字线 目标地址，其中相邻字线与目标字线相邻并由目标地址标识。

公开(公告)号：US20140317338A1

公开(公告)日：2014-10-23

申请号：US14030697

申请日：2013-09-18

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G06F12/02

CPC classification number: G11C7/24 ,  G06F12/023 ,  G11C7/20 ,  G11C29/785 ,  G11C2029/0401 ,  G11C2029/4402

Abstract: A memory device includes a memory cell array having a plurality of memory cells, a storage unit suitable for storing a fail address corresponding to a fail memory cell in the memory cell array, an available storage capacity determination unit suitable for generating available capacity information indicating an available storage capacity in the storage unit, and an output circuit suitable for outputting the available capacity information.

Abstract translation: 存储器件包括具有多个存储器单元的存储单元阵列，适用于存储与存储单元阵列中的故障存储单元相对应的故障地址的存储单元，适用于产生指示存储单元阵列的可用容量信息的可用存储容量确定单元 存储单元中的可用存储容量，以及适于输出可用容量信息的输出电路。

公开(公告)号：US20140078845A1

公开(公告)日：2014-03-20

申请号：US13719906

申请日：2012-12-19

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: G11C11/402 ,  G11C7/20

CPC classification number: G11C11/402 ,  G11C7/02 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4096 ,  G11C2211/4065

Abstract: A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines.

Abstract translation: 存储器包括被配置为包括连接到多个字线的多个第一存储器单元的第一单元阵列，被配置为包括连接到所述多个字线的多个第二存储单元的第二单元阵列，其中， 连接到对应字线的多个第二存储单元存储对应字线的激活次数，以及激活号码更新单元，被配置为更新存储在连接到所述多个第二存储器单元的对应组中的值 激活的多个字线的字线。