公开(公告)号：US11960367B2

公开(公告)日：2024-04-16

申请号：US17751463

申请日：2022-05-23

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Dae Sik Park

IPC: G06F11/20 ,  G06F13/42

CPC classification number: G06F11/2005 ,  G06F13/4221 ,  G06F2201/85 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) device includes a plurality of lanes comprising a plurality of ports, a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes the remaining of lanes, except for a fail lane from among the plurality of lanes, and an EQ controller performing an equalization operation for determining a transmitter or receiver setting of each of the remaining lanes, wherein the EQ controller determining a final EQ coefficient using a log information and an error information.

公开(公告)号：US11940942B2

公开(公告)日：2024-03-26

申请号：US17527062

申请日：2021-11-15

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/4221 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a transaction layer generating a transaction packet for transmission of a transaction, a data link layer generating a link packet including a protection code and a sequence number for the transaction packet and a link packet including a sequence number on the basis of the transaction packet, a physical layer generating a physical packet on the basis of the link packet and sequentially outputting the physical packet, a link training module performing negotiation for a link coupled through the physical layer and maintaining data information based on whether a link down occurring when the negotiation for the link is not performed is requested by a host or not, and a PCIe register storing information about the transaction layer, the data link layer, the physical layer, and the link training module.

公开(公告)号：US11921657B2

公开(公告)日：2024-03-05

申请号：US17749133

申请日：2022-05-19

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Dae Sik Park

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

公开(公告)号：US11841819B2

公开(公告)日：2023-12-12

申请号：US17467054

申请日：2021-09-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon

IPC: G06F13/42 ,  G06F13/28 ,  G06F13/16 ,  G06F9/46

CPC classification number: G06F13/4282 ,  G06F9/466 ,  G06F13/1673 ,  G06F13/28

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) interface device and a method of operating the same. The PCIe interface device includes a first buffer, a second buffer, and a buffer controller. The first buffer may be configured to store a plurality of first transaction layer packets received from multiple functions. The second buffer may be configured to store a plurality of second transaction layer packets received from the multiple functions. The buffer controller may be configured to, when a first buffer of a switch is full, realign an order in which the plurality of second transaction layer packets are to be output from the second buffer to the switch, based on IDs of the plurality of second transaction layer packets.

公开(公告)号：US11815941B2

公开(公告)日：2023-11-14

申请号：US17526995

申请日：2021-11-15

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Dae Sik Park

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/4027 ,  G06F2213/0026

Abstract: A method of operating a Peripheral Component Interconnect Express (PCIe) device including a first port and a second port comprises: performing a first link training operation to link up a first host with a first link of the first port; operating in a single port mode when the first link training operation is completed; performing a lane reduce operation to reduce a lane corresponding to the first link in response to a mode change request received from the first host; and performing a second link training operation to link up a second host with a second link of the second port when a status of the first link is an L0 state.

公开(公告)号：US11782792B2

公开(公告)日：2023-10-10

申请号：US17350885

申请日：2021-06-17

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Dae Sik Park ,  Jae Young Jang

IPC: G06F11/00 ,  G06F11/14 ,  G06F13/42

CPC classification number: G06F11/1443 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A device is provided to include: a transceiver configured to transmit and receive data; and a skip ordered set (SKP OS) control logic in communication with the transceiver and configured to generate an SKP OS and control the transceiver to transmit the SKP OS and a data block to a link connecting to an external device and including a plurality of lanes. The SKP OS control logic is configured to increase or decrease transmission interval of the SKP OS based on a transmission history of the SKP OS, in response to an entry of the link to a recovery state that is used to recover the link from an error.

公开(公告)号：US11782616B2

公开(公告)日：2023-10-10

申请号：US17574266

申请日：2022-01-12

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/065 ,  G06F3/0614 ,  G06F3/0689

Abstract: A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.

公开(公告)号：US11546128B2

公开(公告)日：2023-01-03

申请号：US17349775

申请日：2021-06-16

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Dae Sik Park ,  Jae Young Jang ,  Byung Cheol Kang ,  Seung Duk Cho

IPC: H03D3/24 ,  H04L7/00 ,  H04L7/033

Abstract: Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.