公开(公告)号：US12204779B2

公开(公告)日：2025-01-21

申请号：US18316241

申请日：2023-05-12

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon

IPC: G06F3/06

Abstract: A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.

公开(公告)号：US12007918B2

公开(公告)日：2024-06-11

申请号：US17467070

申请日：2021-09-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Sang Hyun Yoon ,  Se Hyeon Han

IPC: G06F13/00 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) interface device and a method of operating the same. The PCIe interface device may include a performance analyzer and a traffic class controller. The performance analyzer may be configured to measure throughputs of multiple functions executed on one or more Direct Memory Access (DMA) devices. The traffic class controller may be configured to allocate traffic class values to transaction layer packets received from the multiple functions based on the throughputs of the multiple functions.

公开(公告)号：US11928070B2

公开(公告)日：2024-03-12

申请号：US17506610

申请日：2021-10-20

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Byung Cheol Kang ,  Seung Duk Cho ,  Sang Hyun Yoon ,  Se Hyeon Han ,  Jae Young Jang

IPC: G06F13/42 ,  G06F1/08 ,  G06F7/58 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F1/08 ,  G06F7/588 ,  G06F13/4045

Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

公开(公告)号：US12216599B2

公开(公告)日：2025-02-04

申请号：US17567609

申请日：2022-01-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Sang Hyun Yoon ,  Se Hyeon Han

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) device and a method of operating the same. The PCIe device may include a performance analyzer, a delay time information generato and a command fetcher. The performance analyzer may measure throughputs of a plurality of functions, and generate throughput analysis information indicating a comparison result between the throughputs of the plurality of functions and throughput limits corresponding to the plurality of functions. The delay time information generator may generate a delay time for delaying a command fetch operation for each of the plurality of functions based on the throughput analysis information. The command fetcher may fetch a target command from a host based on a delay time of a function corresponding to the target command.

公开(公告)号：US12132814B2

公开(公告)日：2024-10-29

申请号：US17840340

申请日：2022-06-14

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Dae Sik Park ,  Jae Young Jang ,  Byung Cheol Kang ,  Seung Duk Cho

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/00 ,  H04L25/40

CPC classification number: H04L7/005 ,  H04L7/0079 ,  H04L7/0091 ,  H04L7/033

Abstract: Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

公开(公告)号：US11789658B2

公开(公告)日：2023-10-17

申请号：US17522810

申请日：2021-11-09

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0635 ,  G06F3/0679

Abstract: A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.

公开(公告)号：US12159035B2

公开(公告)日：2024-12-03

申请号：US17481503

申请日：2021-09-22

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon

IPC: G06F3/06 ,  G06F13/42

Abstract: An electronic device, and more particularly, a Peripheral Component Interconnect Express (PCIe) interface device is provided. The PCIe interface device includes a root complex configured to support a PCIe port which is a root port that could be coupled to an input/output (I/O) device, a plurality of endpoints each coupled to the root complex through a link, and a Redundant Array of Independent Disks (RAID) controller configured to control RAID-coupling of a plurality of storage devices that are respectively coupled to the plurality of endpoints, wherein the RAID controller requests a host to allocate a capacity to each function in the plurality of storage devices based on a reference capacity.

公开(公告)号：US11874689B2

公开(公告)日：2024-01-16

申请号：US17749133

申请日：2022-05-19

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Dae Sik Park

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

公开(公告)号：US11698736B2

公开(公告)日：2023-07-11

申请号：US17574266

申请日：2022-01-12

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/065 ,  G06F3/0614 ,  G06F3/0689

Abstract: A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.

公开(公告)号：US11599495B2

公开(公告)日：2023-03-07

申请号：US17350945

申请日：2021-06-17

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Dae Sik Park ,  Seung Duk Cho

IPC: G06F13/42

Abstract: Devices for performing communications are disclosed. In some implementations, a device includes: an upstream port for receiving data from or transmitting data to one or more external devices located on an upstream path through a link including a plurality of lanes; a lane margining controller coupled to the upstream port and for transmitting, via the upstream port, to the one or more external devices, a margin command for requesting a lane margining operation to acquire margin status information to indicate a margin of each of the plurality of lanes, and controlling the upstream port to receive the margin status information from the external devices; and a port setting controller coupled to be in communication with the upstream port to receive the margin status information and for determining a setting of the upstream port based on the margin status information.