公开(公告)号：US11874689B2

公开(公告)日：2024-01-16

申请号：US17749133

申请日：2022-05-19

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Dae Sik Park

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

公开(公告)号：US12007918B2

公开(公告)日：2024-06-11

申请号：US17467070

申请日：2021-09-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Sang Hyun Yoon ,  Se Hyeon Han

IPC: G06F13/00 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) interface device and a method of operating the same. The PCIe interface device may include a performance analyzer and a traffic class controller. The performance analyzer may be configured to measure throughputs of multiple functions executed on one or more Direct Memory Access (DMA) devices. The traffic class controller may be configured to allocate traffic class values to transaction layer packets received from the multiple functions based on the throughputs of the multiple functions.

公开(公告)号：US11940942B2

公开(公告)日：2024-03-26

申请号：US17527062

申请日：2021-11-15

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/4221 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a transaction layer generating a transaction packet for transmission of a transaction, a data link layer generating a link packet including a protection code and a sequence number for the transaction packet and a link packet including a sequence number on the basis of the transaction packet, a physical layer generating a physical packet on the basis of the link packet and sequentially outputting the physical packet, a link training module performing negotiation for a link coupled through the physical layer and maintaining data information based on whether a link down occurring when the negotiation for the link is not performed is requested by a host or not, and a PCIe register storing information about the transaction layer, the data link layer, the physical layer, and the link training module.

公开(公告)号：US11921657B2

公开(公告)日：2024-03-05

申请号：US17749133

申请日：2022-05-19

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Dae Sik Park

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

公开(公告)号：US11782497B2

公开(公告)日：2023-10-10

申请号：US17522827

申请日：2021-11-09

Applicant: SK hynix Inc.

Inventor： Ji Woon Yang ,  Yong Tae Jeon

IPC: G06F1/3234 ,  G06F13/42 ,  G06F13/40 ,  G06F1/3206 ,  G06F9/4401

CPC classification number: G06F1/3253 ,  G06F1/3206 ,  G06F13/4022 ,  G06F13/4282 ,  G06F9/4418 ,  G06F2213/0026 ,  Y02D10/00

Abstract: A peripheral component interconnect express (PCIe) interface device is provided to include: a root complex configured to support a PCIe port, a memory connected to an input/output structure through the root complex, a switch connected to the root complex through a link and configured to transmit a transaction, and an end point connected to the switch through the link to transmit and receive a packet. The PCIe interface device may perform a link power management by changing a state of the link in response to a detection of an idle state of the link.

公开(公告)号：US20220309014A1

公开(公告)日：2022-09-29

申请号：US17467070

申请日：2021-09-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Sang Hyun Yoon ,  Se Hyeon Han

IPC: G06F13/24 ,  G06F13/42

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) interface device and a method of operating the same. The PCIe interface device may include a performance analyzer and a traffic class controller. The performance analyzer may be configured to measure throughputs of multiple functions executed on one or more Direct Memory Access (DMA) devices. The traffic class controller may be configured to allocate traffic class values to transaction layer packets received from the multiple functions based on the throughputs of the multiple functions.

公开(公告)号：US12216599B2

公开(公告)日：2025-02-04

申请号：US17567609

申请日：2022-01-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Sang Hyun Yoon ,  Se Hyeon Han

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) device and a method of operating the same. The PCIe device may include a performance analyzer, a delay time information generato and a command fetcher. The performance analyzer may measure throughputs of a plurality of functions, and generate throughput analysis information indicating a comparison result between the throughputs of the plurality of functions and throughput limits corresponding to the plurality of functions. The delay time information generator may generate a delay time for delaying a command fetch operation for each of the plurality of functions based on the throughput analysis information. The command fetcher may fetch a target command from a host based on a delay time of a function corresponding to the target command.

公开(公告)号：US11789658B2

公开(公告)日：2023-10-17

申请号：US17522810

申请日：2021-11-09

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0635 ,  G06F3/0679

Abstract: A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.

公开(公告)号：US11625195B2

公开(公告)日：2023-04-11

申请号：US17372053

申请日：2021-07-09

Applicant: SK hynix Inc.

Inventor： In Ho Jung ,  Ji Woon Yang ,  Gi Jo Jeong ,  Seung Duk Cho

IPC: G06F3/06

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host or head doorbell information for N completion queues capable of storing an execution result of the command fetched from the host.