公开(公告)号：US12087735B2

公开(公告)日：2024-09-10

申请号：US17210743

申请日：2021-03-24

Applicant: SOCIONEXT INC.

Inventor： Hirotaka Takeno ,  Wenzhen Wang ,  Atsushi Okamoto

IPC: H01L25/065 ,  G11C5/14 ,  H01L27/02 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L27/0207 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.

公开(公告)号：US12046598B2

公开(公告)日：2024-07-23

申请号：US17507567

申请日：2021-10-21

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L23/5286 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

公开(公告)号：US11799471B2

公开(公告)日：2023-10-24

申请号：US18069084

申请日：2022-12-20

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Junji Iwahori

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687 ,  H03K19/00

CPC classification number: H03K17/161 ,  H03K17/6871 ,  H03K19/0008

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US20220293634A1

公开(公告)日：2022-09-15

申请号：US17829341

申请日：2022-05-31

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and a second wiring layer formed on a second surface of the substrate opposite to the first surface of the substrate. The second wiring layer includes a first power line to which a first power potential is applied; a second power line to which a second power potential is applied; a third power line to which a third power potential is applied; a first switch connected between the first power line and the second power line; and a second switch provided on one of the first power line or the third power line. The first chip includes a first circuit provided between the first power line and the third power line.