公开(公告)号：US12295168B2

公开(公告)日：2025-05-06

申请号：US18744087

申请日：2024-06-14

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L23/528 ,  H10D30/43 ,  H10D30/67 ,  H10D62/10 ,  H10D84/85

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

公开(公告)号：US12283542B2

公开(公告)日：2025-04-22

申请号：US17577994

申请日：2022-01-18

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto ,  Toshio Hino

IPC: H01L23/528 ,  H01L23/522 ,  H10D89/10

Abstract: A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.

公开(公告)号：US12184282B2

公开(公告)日：2024-12-31

申请号：US17724247

申请日：2022-04-19

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto ,  Wenzhen Wang

IPC: H03K19/173 ,  H01L23/495 ,  H01L23/528 ,  H01L29/78

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

公开(公告)号：US12154904B2

公开(公告)日：2024-11-26

申请号：US17714683

申请日：2022-04-06

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Wenzhen Wang ,  Hirotaka Takeno

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

公开(公告)号：US20190312024A1

公开(公告)日：2019-10-10

申请号：US16448241

申请日：2019-06-21

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/02 ,  H01L27/088 ,  H01L23/528 ,  H01L27/118 ,  H01L27/092 ,  H01L29/10 ,  H03K17/16 ,  H01L29/08 ,  H03K19/00 ,  H01L21/8238

Abstract: A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

公开(公告)号：US12068288B2

公开(公告)日：2024-08-20

申请号：US18179013

申请日：2023-03-06

Applicant: SOCIONEXT INC.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US11563432B2

公开(公告)日：2023-01-24

申请号：US17577701

申请日：2022-01-18

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Junji Iwahori

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US11309248B2

公开(公告)日：2022-04-19

申请号：US17063452

申请日：2020-10-05

Applicant: SOCIONEXT INC.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/78 ,  H03K17/687

Abstract: A power switch cell using vertical nanowire (VNW) FETs includes a switch element configured to be capable of switching between electrical connection and disconnection between a global power interconnect and a local power interconnect. The switch element is constituted by at least one VNW FET. The top electrode of the VNW FET constituting the switch element is connected with the global power interconnect.

公开(公告)号：US11233044B2

公开(公告)日：2022-01-25

申请号：US17014662

申请日：2020-09-08

Applicant: SOCIONEXT INC.

Inventor： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L23/528 ,  H01L29/78 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

公开(公告)号：US10734373B2

公开(公告)日：2020-08-04

申请号：US16189900

申请日：2018-11-13

Applicant: SOCIONEXT INC.

Inventor： Atsushi Okamoto ,  Tomoyasu Kitaura ,  Hirotaka Takeno

IPC: H01L27/02 ,  G06F1/26 ,  H01L27/118 ,  G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  H01L23/528 ,  H03K19/00

Abstract: A circuit block including standard cells (1) arranged therein is provided with switch cells (20) capable of switching between electrical connection and disconnection between power supply lines (3) extending in an X-direction and power supply straps (11) extending in a Y-direction. Each of the power supply straps (11) is provided with a single switch cell (20) arranged every M sets of power supply lines (3) (M is an integer of 3 or more). In the Y-direction, the switch cells (20) are arranged at different positions in the power supply straps (11) adjacent to each other, and are arranged at the same position every M power supply straps (11) in the X-direction.