公开(公告)号：US20150206972A1

公开(公告)日：2015-07-23

申请号：US14675156

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： QING LIU ,  NICOLAS LOUBET

IPC: H01L29/78 ,  H01L21/84 ,  H01L21/225 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

公开(公告)号：US20150102410A1

公开(公告)日：2015-04-16

申请号：US14050666

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES INC ,  STMicroelectronics, Inc.

Inventor： QING LIU ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/6653 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/78684

Abstract: A method for making a semiconductor device may include forming a gate on a semiconductor layer, forming sidewall spacers adjacent the gate, and forming raised source and drain regions defining a channel in the semiconductor layer under the gate. The raised source and drain regions may be spaced apart from the gate by the sidewall spacers. The method may further include removing the sidewall spacers to expose the semiconductor layer between the raised source and drain regions and the gate, and forming a stress layer overlying the gate and the raised source and drain regions. The stress layer may contact the semiconductor layer between the raised source and drain regions and the gate.

Abstract translation: 制造半导体器件的方法可以包括在半导体层上形成栅极，在栅极附近形成侧壁间隔物，以及形成在栅极下方的半导体层中限定沟道的凸起的源极和漏极区域。 升高的源极和漏极区域可以通过侧壁间隔物与栅极间隔开。 该方法还可以包括移除侧壁间隔物以暴露凸起的源极和漏极区域和栅极之间的半导体层，并且形成覆盖栅极和升高的源极和漏极区域的应力层。 应力层可以接触凸起的源极和漏极区域与栅极之间的半导体层。

公开(公告)号：US20140377923A1

公开(公告)日：2014-12-25

申请号：US14478347

申请日：2014-09-05

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： QING LIU ,  JUNLI WANG

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/82 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.