公开(公告)号：US20140353716A1

公开(公告)日：2014-12-04

申请号：US13906789

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC

Inventor： NICOLAS LOUBET ,  PRASANNA KHARE

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

Abstract translation: 制造半导体器件的方法包括在半导体层上形成翅片掩模层，在鳍掩模层上形成虚拟栅极，以及在虚拟栅极的相对侧上形成源极和漏极区域。 去除虚拟栅极并且使用底层翅片掩模层来在半导体层中限定多个散热片。 在多个翅片上形成闸门。

公开(公告)号：US20160118387A1

公开(公告)日：2016-04-28

申请号：US14982037

申请日：2015-12-29

Applicant: STMICROELECTRONICS, INC.

Inventor： QING LIU ,  NICOLAS LOUBET

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78603

Abstract: A method for making a semiconductor device includes forming a buried oxide stack on a semiconductor wafer. The buried oxide stack includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. A semiconductor layer is formed on the second oxide layer. First and second channel regions are formed in the semiconductor layer.

公开(公告)号：US20160064566A1

公开(公告)日：2016-03-03

申请号：US14939729

申请日：2015-11-12

Applicant: STMICROELECTRONICS, INC.

Inventor： NICOLAS LOUBET ,  PIERRE MORIN

IPC: H01L29/78 ,  H01L29/165 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795

Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

Abstract translation: 制造半导体器件的方法包括在第一半导体材料层上形成用于至少一个栅极叠层的第一间隔物，以及与邻近所述至少一个栅极的每个源区和漏区形成相应的第二间隔物。 每个第二间隔件具有一对相对的侧壁和与其连接的端壁。 该方法包括用第二半导体材料填充源区和漏区，而第一和第二间隔件提供约束。

公开(公告)号：US20160020154A1

公开(公告)日：2016-01-21

申请号：US14867797

申请日：2015-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： KANGGUO CHENG ,  BRUCE B. DORIS ,  ALI KHAKIFIROOZ ,  QING LIU ,  NICOLAS LOUBET ,  SCOTT LUNING

IPC: H01L21/84 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

公开(公告)号：US20150236050A1

公开(公告)日：2015-08-20

申请号：US14182601

申请日：2014-02-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： NICOLAS LOUBET ,  James KUSS

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/161 ,  H01L29/06 ,  H01L21/02 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L27/1211 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/78696

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins. The method may further include forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer, with the first group of nanowires including the first semiconductor material and the second group of nanowires including the second semiconductor material.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成多个翅片，在第一组翅片的侧面上形成第一半导体材料，并在第二组翅片的侧面上形成第二半导体材料 。 该方法还可以包括形成覆盖多个翅片的介电层，以限定电介质层内的第一和第二组纳米线，第一组纳米线包括第一半导体材料，第二组纳米线包括第二半导体材料。

公开(公告)号：US20150206972A1

公开(公告)日：2015-07-23

申请号：US14675156

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： QING LIU ,  NICOLAS LOUBET

IPC: H01L29/78 ,  H01L21/84 ,  H01L21/225 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

公开(公告)号：US20150054032A1

公开(公告)日：2015-02-26

申请号：US14518590

申请日：2014-10-20

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： NICOLAS LOUBET ,  DOUGLAS LATULIPE ,  ALEXANDER REZNICEK

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.

Abstract translation: 制造半导体器件的方法包括在包括第一半导体材料的层上形成至少一个栅极堆叠，以及邻近所述至少一个栅极堆叠的蚀刻源极和漏极凹陷。 该方法进一步包括成形源极和漏极凹槽以具有从底部向上延伸到与所述至少一个栅极堆叠相邻的倾斜延伸部的垂直侧。

公开(公告)号：US20140357029A1

公开(公告)日：2014-12-04

申请号：US13906758

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC.

Inventor： NICOLAS LOUBET ,  Prasanna Khare

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878

Abstract: A method of making a semiconductor device includes forming a sacrificial layer above a semiconductor layer. Portions of the sacrificial layer are selectively removed to define a first set of spaced apart sacrificial fins over a first region of the semiconductor layer, and a second set of spaced apart sacrificial fins over a second region of the semiconductor layer. An isolation trench is formed in the semiconductor layer between the first and second regions. The isolation trench and spaces are filled with a dielectric material. The first and second sets of sacrificial fins are removed to define respective first and second sets of fin openings. The first set of fin openings is filled to define a first set of semiconductor fins for a first conductivity-type transistor, and the second set of fin openings is filled to define a second set of semiconductor fins for a second conductivity-type transistor.

Abstract translation: 制造半导体器件的方法包括在半导体层上形成牺牲层。 牺牲层的一部分被选择性地去除以在半导体层的第一区域上限定出第一组隔开的牺牲散热片，以及在半导体层的第二区域上的第二组隔开的牺牲散热片。 在第一和第二区域之间的半导体层中形成隔离沟槽。 绝缘沟槽和空间填充有电介质材料。 去除第一组和第二组牺牲翅片以限定相应的第一组和第二组翅片开口。 填充第一组翅片开口以限定用于第一导电型晶体管的第一组半导体鳍片，并且填充第二组翅片开口以限定用于第二导电型晶体管的第二组半导体鳍片。

公开(公告)号：US20170170299A1

公开(公告)日：2017-06-15

申请号：US15437487

申请日：2017-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： STEPHANE ALLEGRET-MARET ,  KANGGUO CHENG ,  BRUCE DORIS ,  PRASANNA KHARE ,  QING LIU ,  NICOLAS LOUBET

IPC: H01L29/66 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L29/66772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.

公开(公告)号：US20160079128A1

公开(公告)日：2016-03-17

申请号：US14955801

申请日：2015-12-01

Applicant: STMICROELECTRONICS, INC. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： NICOLAS LOUBET ,  SYLVAIN MAITREJEAN ,  ROMAIN WACQUEZ

IPC: H01L21/84 ,  H01L21/266 ,  H01L21/306 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.