公开(公告)号：US20180247901A1

公开(公告)日：2018-08-30

申请号：US15698882

申请日：2017-09-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L23/00 ,  H01L29/06

CPC classification number: H01L23/573 ,  H01L23/576 ,  H01L29/0649

Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.

公开(公告)号：US12230565B2

公开(公告)日：2025-02-18

申请号：US18437720

申请日：2024-02-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L29/66 ,  H01L21/762 ,  H01L23/522 ,  H01L27/08

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US12198973B2

公开(公告)日：2025-01-14

申请号：US18127751

申请日：2023-03-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Abderrezak Marzaki

IPC: H01L25/16 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L25/18

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

公开(公告)号：US11942440B2

公开(公告)日：2024-03-26

申请号：US17091466

申请日：2020-11-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Abderrezak Marzaki

IPC: H01L23/00 ,  G06F21/55 ,  G06F21/78 ,  G06F21/87 ,  H01L29/06 ,  H04L9/00

CPC classification number: H01L23/576 ,  G06F21/556 ,  G06F21/78 ,  G06F21/87 ,  H01L29/0646 ,  H01L29/0649 ,  H04L9/004 ,  H04L2209/12

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.

公开(公告)号：US11605702B2

公开(公告)日：2023-03-14

申请号：US17165013

申请日：2021-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L27/11517 ,  H01L29/06 ,  H01L27/06 ,  H01L27/07 ,  H01L49/02 ,  H01L27/10 ,  H01L27/08

Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

公开(公告)号：US10943973B2

公开(公告)日：2021-03-09

申请号：US16400286

申请日：2019-05-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L27/115 ,  H01L27/06 ,  H01L27/07 ,  H01L27/08 ,  H01L27/10 ,  H01L29/06 ,  H01L49/02 ,  H01L27/11517

Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

公开(公告)号：US10804223B2

公开(公告)日：2020-10-13

申请号：US16139370

申请日：2018-09-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L23/00 ,  H01L29/06

Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.

公开(公告)号：US10770409B2

公开(公告)日：2020-09-08

申请号：US16051680

申请日：2018-08-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Christian Rivero ,  Quentin Hubert

IPC: G06K19/073 ,  G06F21/75 ,  H01L23/00 ,  H01L27/02

Abstract: An integrated electronic circuit includes a semiconductor substrate with a semiconductor well that is isolated by a buried semiconductor region located under the semiconductor well. A vertical MOS transistor formed in the semiconductor well includes a source-drain region provided by the buried semiconductor region. Backside thinning of the semiconductor substrate is detected by biasing the vertical MOS transistor into an on condition to supply a current and then comparing that current to a threshold. Current less than a threshold is indicative that the semiconductor substrate has been thinned from the backside.

公开(公告)号：US10651184B2

公开(公告)日：2020-05-12

申请号：US16708165

申请日：2019-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L27/11524 ,  H01L27/06 ,  H01L29/06 ,  H01L29/94 ,  H01L29/66 ,  H01L27/11531 ,  H01L21/8234

Abstract: A well of a first conductivity type is insulated from a substrate of the same first conductivity type by a structure of a triple well type. The structure includes a trench having an electrically conductive central part enclosed in an insulating sheath. The trench supports a first electrode of a decoupling capacitor, with a second electrode provided by the well.

公开(公告)号：US10453808B2

公开(公告)日：2019-10-22

申请号：US16129163

申请日：2018-09-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Abderrezak Marzaki

IPC: H01L23/00 ,  H01L21/66 ,  H01L29/861 ,  H01L29/06

Abstract: An electronic integrated circuit includes a semiconductor substrate having a rear face. A device for detecting a thinning of the semiconductor substrate via its rear face is formed by a p-n junction that is biased into conduction. Thinning of the substrate is detected by monitoring a current flowing through the p-n junction, and comparing that current to a threshold. In the event the compared current indicates no thinning of the semiconductor substrate, the circuitry for biasing and comparing is deactivated.