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公开(公告)号：US20210281497A1
公开(公告)日：2021-09-09
申请号：US17182914
申请日：2021-02-23
Applicant: STMicroelectronics Application GMBH
Inventor： Fred Rennig
IPC: H04L12/26
Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.
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公开(公告)号：US20190294572A1
公开(公告)日：2019-09-26
申请号：US16360229
申请日：2019-03-21
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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23.发明申请BUS MICROCONTROLLER, BUS NODE CIRCUIT AND ELECTRONIC CONTROL UNIT FOR A VEHICLE 有权总线微控制器，总线电路和电子控制单元公开(公告)号：US20150192983A1
公开(公告)日：2015-07-09
申请号：US14591779
申请日：2015-01-07
Applicant: STMicroelectronics Application GmbH
Inventor： Fred Rennig
IPC: G06F1/32
CPC classification number: G06F1/3243 , G06F1/3209 , G06F1/3234 , G06F1/3287 , G06F1/3293 , H04L12/403 , Y02D10/10
Abstract: A bus microcontroller includes a processor circuit having at least one unit designed for performing one or more functions due to a bus command via a communication bus, a power control circuit adapted to be coupled to a transmitter-receiver circuit for receiving bus messages via the communication bus, and a means for placing at least part of the processor circuit into a reduced-power operating mode without placing the entire processor circuit into the reduced-power operating mode. The power control circuit is designed to evaluate incoming bus messages with respect to an activation bus message containing information on activating at least part of the processor circuit, and to output a corresponding activation control signal. The bus microcontroller also includes means for activating at least a part of the processor circuit that is placed in a reduced-power operating mode, in response to output of an activation control signal of the power control circuit.
Abstract translation: 总线微控制器包括具有至少一个单元的处理器电路，该至少一个单元被设计用于通过通信总线由总线命令执行一个或多个功能;功率控制电路，适于耦合到发送器 - 接收器电路，用于经由通信接收总线消息 总线，以及用于将处理器电路的至少一部分放置在降低功率操作模式而不使整个处理器电路进入降低功率操作模式的手段。 功率控制电路被设计为针对包含关于激活至少部分处理器电路的信息的激活总线消息来评估输入总线消息，并且输出相应的激活控制信号。 总线微控制器还包括用于响应于功率控制电路的激活控制信号的输出而激活放置在降低功率工作模式的处理器电路的至少一部分的装置。
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公开(公告)号：US12066962B2
公开(公告)日：2024-08-20
申请号：US18309103
申请日：2023-04-28
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G05B19/042 , G06F9/54 , G06F11/07 , G06F11/10 , G06F13/40 , G06F13/42 , H04L12/40 , H04L12/403 , H03M13/09
CPC classification number: G06F13/362 , G05B19/042 , G06F9/542 , G06F11/0739 , G06F11/0757 , G06F11/0772 , G06F11/1004 , G06F13/4068 , G06F13/4282 , H04L12/40006 , H04L12/40013 , H04L12/40078 , H04L12/403 , G05B2219/1215 , G05B2219/2231 , G05B2219/31179 , H03M13/09 , H04L2012/40215
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US20240048405A1
公开(公告)日：2024-02-08
申请号：US18489590
申请日：2023-10-18
Inventor： Vaclav Dvorak , Fred Rennig
CPC classification number: H04L12/40013 , G06F13/423 , H04L12/40169 , H04L2012/40215
Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.
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Patent Agency Ranking
26.发明公开公开(公告)号：US20240048404A1
公开(公告)日：2024-02-08
申请号：US18350345
申请日：2023-07-11
Applicant: STMicroelectronics Application GMBH
Inventor： Fred Rennig
IPC: H04L12/40
CPC classification number: H04L12/40006 , H04L2012/40215
Abstract: An electronic device includes a CAN protocol controller, a first communication port configured to be coupled to a first segment of a differential bus, and a second communication port configured to be coupled to a second segment of the differential bus. A first CAN transceiver circuit is coupled to the CAN protocol controller and is configured to receive a first CAN transmission signal and to transmit a first CAN reception signal. The first CAN transceiver is configured to drive a differential voltage at the first segment of the differential bus based on the first CAN transmission signal and to sense a differential voltage at the first segment of the differential bus. The second communication port is enabled in response to a control signal being de-asserted and disabled in response to the control signal being asserted.
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公开(公告)号：US11824681B2
公开(公告)日：2023-11-21
申请号：US17814113
申请日：2022-07-21
Inventor： Vaclav Dvorak , Fred Rennig
CPC classification number: H04L12/40013 , G06F13/423 , H04L12/40169 , H04L2012/40215
Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.
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公开(公告)号：US20230269150A1
公开(公告)日：2023-08-24
申请号：US18309397
申请日：2023-04-28
Applicant: STMicroelectronics Application GMBH
Inventor： Fred Rennig
IPC: H04L43/08
Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.
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公开(公告)号：US20230053564A1
公开(公告)日：2023-02-23
申请号：US17814113
申请日：2022-07-21
Inventor： Vaclav Dvorak , Fred Rennig
Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.
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公开(公告)号：US20200272589A1
公开(公告)日：2020-08-27
申请号：US16874055
申请日：2020-05-14
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40 , G06F11/07 , H04L12/403 , G05B19/042
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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