公开(公告)号：US20160349824A1

公开(公告)日：2016-12-01

申请号：US15232506

申请日：2016-08-09

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  STEPHAN GASKINS

IPC: G06F1/32 ,  G06F9/30 ,  G06F12/084 ,  G06F1/12 ,  G06F13/24 ,  G06F12/0875 ,  G06F9/38 ,  G06F1/04

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

公开(公告)号：US09052359B2

公开(公告)日：2015-06-09

申请号：US12917947

申请日：2010-11-02

Applicant: Samuel D. Naffziger ,  Suresh B. Periyacheri

Inventor： Samuel D. Naffziger ,  Suresh B. Periyacheri

IPC: G06F1/32 ,  G01R31/317

CPC classification number: G01R31/31721 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  Y02D10/00 ,  Y02D10/10

Abstract: A method and system for varying sampling frequency to avoid software harmonics when sampling digital power indicators are described herein. A power monitor may repetitively sample, at a variable sampling rate based on a variable delay time, multiple signals of an IC device to obtain energy values. The variable delay time may be based on a pseudo-random value or a predictable value. The variable delay time may indicate a number of delay cycles that may be inserted between the repetitive samples of the energy values. The variable number of delay cycles between energy value samples may produce a variable sampling rate. A variable sampling rate may avoid alignment with software harmonics which can cause an inaccurate representation of power consumption. The multiple samples obtained by repetitively sampling energy value for the portion of the IC may be summed to generate a cumulative energy value for the portion of the IC.

Abstract translation: 本文描述了在采样数字功率指示器时改变采样频率以避免软件谐波的方法和系统。 功率监视器可以基于可变延迟时间的可变采样率重复采样IC器件的多个信号以获得能量值。 可变延迟时间可以基于伪随机值或可预测值。 可变延迟时间可以指示可以插入在能量值的重复样本之间的延迟周期的数量。 能量值样本之间可变数量的延迟周期可能产生可变采样率。 可变采样率可能避免与软件谐波的对准，这可能导致功耗不准确的表示。 通过对IC的该部分的能量值进行重复取样而获得的多个样本可以相加以产生IC的该部分的累积能量值。

公开(公告)号：US20150067307A1

公开(公告)日：2015-03-05

申请号：US14281796

申请日：2014-05-19

Applicant: Via Technologies, Inc.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/30

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

Abstract translation: 一种微处理器，多个处理核心，其中所述多个处理核心中的每一个都实例化相应的体系结构可视存储资源。 多个处理核心的第一核心被配置为遇到指令第一核心以由架构指令指定的值来更新第一核心的各个架构可见存储资源的架构指令。 第一核还被配置为响应于遇到结构指令而向多个处理核心中的另一个处理核心中的每一个提供该值，并用该值来更新第一核心的相应的架构可见存储资源。 除了第一核心之外的多个处理核心的每个核心被配置为利用由第一核心提供的值来更新核心的各个体系结构可见的存储资源，而不会遇到建筑指令。

公开(公告)号：US20120105050A1

公开(公告)日：2012-05-03

申请号：US12917947

申请日：2010-11-02

Applicant: Samuel D. Naffziger ,  Suresh B. Periyacheri

Inventor： Samuel D. Naffziger ,  Suresh B. Periyacheri

IPC: G01R19/00

CPC classification number: G01R31/31721 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  Y02D10/00 ,  Y02D10/10

Abstract: A method and system for varying sampling frequency to avoid software harmonics when sampling digital power indicators are described herein. A power monitor may repetitively sample, at a variable sampling rate based on a variable delay time, multiple signals of an IC device to obtain energy values. The variable delay time may be based on a pseudo-random value or a predictable value. The variable delay time may indicate a number of delay cycles that may be inserted between the repetitive samples of the energy values. The variable number of delay cycles between energy value samples may produce a variable sampling rate. A variable sampling rate may avoid alignment with software harmonics which can cause an inaccurate representation of power consumption. The multiple samples obtained by repetitively sampling energy value for the portion of the IC may be summed to generate a cumulative energy value for the portion of the IC.

Abstract translation: 本文描述了在采样数字功率指示器时改变采样频率以避免软件谐波的方法和系统。 功率监视器可以基于可变延迟时间的可变采样率重复采样IC器件的多个信号以获得能量值。 可变延迟时间可以基于伪随机值或可预测值。 可变延迟时间可以指示可以插入在能量值的重复样本之间的延迟周期的数量。 能量值样本之间可变数量的延迟周期可能产生可变采样率。 可变采样率可能避免与软件谐波的对准，这可能导致功耗不准确的表示。 通过对IC的该部分的能量值进行重复取样而获得的多个样本可以相加以产生IC的该部分的累积能量值。

公开(公告)号：US09891928B2

公开(公告)日：2018-02-13

申请号：US15232506

申请日：2016-08-09

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F15/76 ,  G06F1/04 ,  G06F1/12 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

公开(公告)号：US09891927B2

公开(公告)日：2018-02-13

申请号：US14281551

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Stephan Gaskins

IPC: G06F1/00 ,  H04L29/06 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

公开(公告)号：US20170308145A1

公开(公告)日：2017-10-26

申请号：US15510261

申请日：2014-12-12

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： Deming GU ,  Zhou HONG

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/32 ,  G06F1/3234 ,  G06T2200/28 ,  Y02D10/10

Abstract: A graphics processing system and a power gating method thereof is provided. The graphics processing system includes a bus interface, a graphics processing unit, and a power management unit. The graphics processing unit includes a plurality of partitions and a control circuit. When the bus interface has received an external graphics processing command, the bus interface informs the power management unit to turn on power to the control circuit. The control circuit turns on power to one or more of the partitions corresponding to the external graphics processing command after analyzing the external graphics processing command. The control circuit turns off power to the partitions in the idle state when detecting that one of the partitions is in the idle state. The bus interface turns off the power to the control circuit via the power management circuit when detecting that the partitions are in a full idle state.

公开(公告)号：US09727435B2

公开(公告)日：2017-08-08

申请号：US14746283

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Samuel D. Naffziger ,  Suresh B. Periyacheri

IPC: G06F1/32 ,  G06F19/00 ,  G01R21/00 ,  G01R31/317 ,  G06F11/30 ,  G01R21/133

CPC classification number: G06F11/3062 ,  G01R21/133 ,  G01R31/31721 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  Y02D10/00 ,  Y02D10/10

Abstract: A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.

公开(公告)号：US09471133B2

公开(公告)日：2016-10-18

申请号：US14281758

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F12/08 ,  G06F1/32 ,  G06F1/04 ,  G06F1/12 ,  G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F13/24

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores.

Abstract translation: 微处理器包括多个处理核心，服务处理单元和可由服务处理单元和多个处理核心访问的存储器。 多个处理核心中的至少一个被配置为将补丁写入存储器。 所述补丁包括要从所述存储器中取出并由所述服务处理单元在由所述多个处理核心中的至少一个写入所述存储器之后执行的一个或多个指令。

公开(公告)号：US20150286550A1

公开(公告)日：2015-10-08

申请号：US14746283

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Samuel D. Naffziger ,  Suresh B. Periyacheri

IPC: G06F11/30 ,  G01R21/133

CPC classification number: G06F11/3062 ,  G01R21/133 ,  G01R31/31721 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  Y02D10/00 ,  Y02D10/10

Abstract: A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.

Abstract translation: 本文描述了通过IC的该部分的工作频率自动缩放由集成电路（IC）器件的一部分消耗的数字功率的估计的方法。 该方法可以包括获得可以对应于IC的该部分使用的能量的量的能量值。 可以通过以与IC的该部分的工作频率成比例的频率重复地产生累积能量值，获得能量值并将每个获得的能量值加到IC的该部分的能量值之和。 可以在时间采样间隔对累积能量值进行采样，以产生IC的数字功率消耗的部分的估计，该部分由IC部分的工作频率自动缩放。