公开(公告)号：US20230246100A1

公开(公告)日：2023-08-03

申请号：US18158986

申请日：2023-01-24

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO ,  Filippo GIANNAZZO ,  Giuseppe Greco ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/285 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/3205

CPC classification number: H01L29/7786 ,  H01L29/66431 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42316 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/0272 ,  H01L21/28506 ,  H01L21/3086 ,  H01L21/3081 ,  H01L21/3065 ,  H01L21/32051

Abstract: An enhancement mode high electron-mobility transistor (HEMT) device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas, 2DEG. The HEMT device includes a gate structure which extends on the top surface of the semiconductor body, is biasable to electrically control the 2DEG and includes a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is of conductive material and the functional layer is of two-dimensional semiconductor material and includes a first doped portion with P-type electrical conductivity, which extends on the top surface of the semiconductor body and is interposed between the semiconductor body and the gate contact along a first axis.

公开(公告)号：US20220130990A1

公开(公告)日：2022-04-28

申请号：US17571334

申请日：2022-01-07

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando IUCOLANO ,  Alfonso PATTI

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L29/10 ,  H01L21/02 ,  H01L29/205 ,  H01L29/417

Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.

公开(公告)号：US20200091313A1

公开(公告)日：2020-03-19

申请号：US16690035

申请日：2019-11-20

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Alfonso PATTI ,  Alessandro Chini

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/423

Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

公开(公告)号：US20190355842A1

公开(公告)日：2019-11-21

申请号：US16526915

申请日：2019-07-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US20190288100A1

公开(公告)日：2019-09-19

申请号：US16431642

申请日：2019-06-04

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Alessandro CHINI

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06 ,  H01L29/205 ,  H01L29/40

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

公开(公告)号：US20250040173A1

公开(公告)日：2025-01-30

申请号：US18912488

申请日：2024-10-10

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando IUCOLANO ,  Alessandro Chini

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

公开(公告)号：US20250022947A1

公开(公告)日：2025-01-16

申请号：US18781815

申请日：2024-07-23

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando IUCOLANO

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

公开(公告)号：US20210273087A1

公开(公告)日：2021-09-02

申请号：US17322528

申请日：2021-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L23/29 ,  H01L23/31

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

公开(公告)号：US20210125834A1

公开(公告)日：2021-04-29

申请号：US17083181

申请日：2020-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando IUCOLANO ,  Cristina TRINGALI

IPC: H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/778 ,  H01L21/3213 ,  H01L29/66

Abstract: A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

公开(公告)号：US20210091218A1

公开(公告)日：2021-03-25

申请号：US17115459

申请日：2020-12-08

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO ,  Alessandro CHINI

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.