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公开(公告)号：US11048525B2
公开(公告)日：2021-06-29
申请号：US16273704
申请日：2019-02-12
Inventor： Roberto Colombo , Om Ranjan
Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration data client.
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公开(公告)号：US11977438B2
公开(公告)日：2024-05-07
申请号：US17406910
申请日：2021-08-19
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
CPC classification number: G06F11/0784 , G06F11/0721 , G06F11/0739 , G06F11/0751 , G06F11/0772 , G06F11/1048
Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.
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公开(公告)号：US20230065623A1
公开(公告)日：2023-03-02
申请号：US17815807
申请日：2022-07-28
Inventor： Vivek Mohan Sharma , Roberto Colombo
Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
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公开(公告)号：US20220382695A1
公开(公告)日：2022-12-01
申请号：US17747800
申请日：2022-05-18
Applicant: STMicroelectronics Application GMBH
Inventor： Rolf Nandlinger , Roberto Colombo
Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.
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公开(公告)号：US20220308892A1
公开(公告)日：2022-09-29
申请号：US17654537
申请日：2022-03-11
IPC: G06F9/4401 , G06F9/30
Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.
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Patent Agency Ranking
公开(公告)号：US10949570B2
公开(公告)日：2021-03-16
申请号：US16039103
申请日：2018-07-18
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
Abstract: In an embodiment, a processing system includes a non-volatile memory, a hardware block, a protection circuit associated with the hardware block, and a password verification circuit. The non-volatile memory stores at least one reference password. The password verification circuit is configured to receive a password verification command, obtain a reference password, and test whether the passwords correspond. In case the passwords correspond, the password verification circuit generate an overwrite signal. The protection circuit is configured to receive a control command and selectively forward the control command to the associated hardware block as a function of the overwrite signal.
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公开(公告)号：US20200348890A1
公开(公告)日：2020-11-05
申请号：US16932426
申请日：2020-07-17
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
Abstract: A processing system comprises a processing unit, a hardware block configured to change operation as a function of life cycle data, and a one-time programmable memory storing original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory, to store the original life cycle data in a register, to receive a write request from the processing unit, and to selectively execute the write request to overwrite the original life cycle data with new life cycle data in the register.
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公开(公告)号：US20200169459A1
公开(公告)日：2020-05-28
申请号：US16679796
申请日：2019-11-11
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
IPC: H04L12/24 , H03K19/177 , H04L29/06 , H04L29/08
Abstract: A hardware configuration circuit can sequentially read data packets from a non-volatile memory. For a first data packet, the circuit is configured to store the configuration data and the address included in the data packet in the register, select a target configuration data client circuit as a function of the address included in the first data packet, transmit a first data signal that includes the configuration data included in the first data packet to the target configuration data client circuit, receive a second data signal that includes configuration data stored in the target configuration data client circuit and the address associated with the target configuration data client circuit, and compare the configuration data and address received from the target configuration data client circuit with the configuration data and address stored in the register.
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公开(公告)号：US20200167220A1
公开(公告)日：2020-05-28
申请号：US16693103
申请日：2019-11-22
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
IPC: G06F11/07
Abstract: A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.
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公开(公告)号：US20180357012A1
公开(公告)日：2018-12-13
申请号：US16002534
申请日：2018-06-07
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F9/30
Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.
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