公开(公告)号：US20170186759A1

公开(公告)日：2017-06-29

申请号：US15133394

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/115 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L27/11546 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/823468 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11541 ,  H01L28/00 ,  H01L28/60 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US09298205B2

公开(公告)日：2016-03-29

申请号：US14024876

申请日：2013-09-12

Applicant: STMicroelectronics Crolles 2 SAS

Inventor： Raul Andres Bianchi

IPC: G05F3/24 ,  G01K7/01 ,  H01L27/12

CPC classification number: G05F3/245 ,  G01K7/01 ,  H01L27/1203

Abstract: An electronic circuit for providing a voltage or a current linearly dependent on temperature within a temperature range, including at least two identical MOS transistors conducting the same drain current, each transistor having a fully depleted channel which is separated from a doped semiconductor region by an insulating layer, the conductive types of the dopants of said doped semiconductor regions being different, said voltage or said current being proportional to the difference between the gate-source/drain voltages of the two transistors.

Abstract translation: 一种电子电路，用于在包括至少两个相同的漏极电流的相同的MOS晶体管的温度范围内提供线性上依赖于温度的电压或电流，每个晶体管具有完全耗尽的通道，其通过绝缘体与掺杂半导体区域分离 所述掺杂半导体区域的掺杂剂的导电类型不同，所述电压或所述电流与两个晶体管的栅极 - 源极/漏极电压之间的差异成比例。

公开(公告)号：US20130099322A1

公开(公告)日：2013-04-25

申请号：US13659768

申请日：2012-10-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Emmanuel Perrin ,  Gregory Bidal ,  Raul Andres Bianchi

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L21/76237 ,  H01L21/28229 ,  H01L21/823481 ,  H01L29/513 ,  H01L29/518

Abstract: A method for defining an insulating area in a semiconductor substrate, including a step of forming of a bonding layer on the walls and the bottom of a trench defined in the substrate. A step of passivation of the apparent surface of said bonding layer, at least close to the surface of said semiconductor substrate.

Abstract translation: 一种用于限定半导体衬底中的绝缘区域的方法，包括在衬底中限定的沟槽的壁和底部上形成接合层的步骤。 至少靠近所述半导体衬底的表面钝化所述接合层的表观表面的步骤。