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公开(公告)号：US12256590B2
公开(公告)日：2025-03-18
申请号：US17543004
申请日：2021-12-06
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Thierry Berger , Stephane Allegret-Maret
Abstract: A pixel includes a first electrode layer on an exposed surface of an interconnection structure and in contact with a conductive element of the interconnection structure. An insulating layer extends over the first electrode layer and includes opening crossing through the insulating layer to the first electrode layer. A second electrode layer is on top of and in contact with the first electrode layer and the insulating layer in the opening. A film configured to convert photons into electron-hole pairs is on the insulating layer, the second electrode layer and filling the opening. A third electrode layer covers the film.
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公开(公告)号：US12224302B2
公开(公告)日：2025-02-11
申请号：US16862316
申请日：2020-04-29
Inventor： Jeff M. Raynor , Frederic Lalanne , Pierre Malinge
IPC: H01L27/146 , H04N25/77 , H04N25/53
Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.
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公开(公告)号：US12144187B2
公开(公告)日：2024-11-12
申请号：US18335940
申请日：2023-06-15
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Remy Berthelon , Olivier Weber
IPC: H10B63/00
Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.
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公开(公告)号：US20240332324A1
公开(公告)日：2024-10-03
申请号：US18739927
申请日：2024-06-11
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Francois ROY
IPC: H01L27/146 , H04N25/53 , H04N25/621 , H04N25/705 , H04N25/75 , H04N25/77
CPC classification number: H01L27/14603 , H01L27/1463 , H04N25/53 , H04N25/621 , H04N25/705 , H04N25/75 , H04N25/77
Abstract: A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.
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5.发明公开公开(公告)号：US20240274552A1
公开(公告)日：2024-08-15
申请号：US18625631
申请日：2024-04-03
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Didier DUTARTRE
IPC: H01L23/66 , H01L21/762 , H01L29/06
CPC classification number: H01L23/66 , H01L21/76286 , H01L29/0646 , H01L29/0649 , H01L2223/6688
Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.
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Patent Agency Ranking
公开(公告)号：US20240186090A1
公开(公告)日：2024-06-06
申请号：US18193230
申请日：2023-03-30
Applicant: STMICROELECTRONICS SA , STMicroelectronics (Crolles 2) SAS , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Inventor： Philippe CATHELIN , Frederic GIANESELLO , Alain FLEURY , Stephane MONFRAY , Bruno REIG , Vincent PUYAL
CPC classification number: H01H37/34 , H10N70/231 , H10N70/826 , H10N70/8413 , H10N70/882
Abstract: The present description concerns a switch based on a phase-change material comprising: first, second, and third electrodes; a first region of said phase-change material coupling the first and second electrodes; and —a second region of said phase-change material coupling the second and third electrodes.
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公开(公告)号：US20240176129A1
公开(公告)日：2024-05-30
申请号：US18193223
申请日：2023-03-30
Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMicroelectronics (Crolles 2) SAS
Inventor： Sandrine VILLENAVE , Quentin ABADIE
CPC classification number: G02B26/001 , G01J3/26 , G02B5/28
Abstract: The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, at least one resonant cavity comprising a transparent region having a first refraction index and laterally delimited by a reflective peripheral vertical wall, and at least one resonant element formed in said region.
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公开(公告)号：US11984360B2
公开(公告)日：2024-05-14
申请号：US17728088
申请日：2022-04-25
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Gregory Avenier , Alexis Gauthier , Pascal Chevalier
IPC: H01L21/82 , H01L21/3105 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L29/66 , H01L29/737 , H01L29/93
CPC classification number: H01L21/8222 , H01L21/31056 , H01L21/8249 , H01L27/0664 , H01L29/66174 , H01L29/66242 , H01L29/7371 , H01L29/93
Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.
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9.发明公开公开(公告)号：US20240153557A1
公开(公告)日：2024-05-09
申请号：US18535335
申请日：2023-12-11
Applicant: Universite D'Aix Marseille , Centre National de la Recherche Scientifique , STMicroelectronics (Crolles 2) SAS
Inventor： Jean-Michel PORTAL , Vincenzo DELLA MARCA , Jean-Pierre WALDER , Julien GASQUEZ , Philippe BOIVIN
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2013/0054 , G11C2213/72
Abstract: A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.
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公开(公告)号：US11957067B2
公开(公告)日：2024-04-09
申请号：US17328917
申请日：2021-05-24
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H10N70/231 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/061 , H10N70/253 , H10N70/823 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/8828 , G11C13/0004 , G11C2213/79 , G11C2213/82
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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