公开(公告)号：US07363561B2

公开(公告)日：2008-04-22

申请号：US11117736

申请日：2005-04-29

申请人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrögmeier

发明人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrögmeier

IPC分类号： G01R31/28

CPC分类号： G06F1/24 ,  H03K5/1534

摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

摘要翻译： 本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路 电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。 本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

公开(公告)号：US06804165B2

公开(公告)日：2004-10-12

申请号：US10374657

申请日：2003-02-26

申请人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Kieser ,  Pramod Acharya

发明人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Kieser ,  Pramod Acharya

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)

摘要翻译： 用于产生用于通过S-DRAM的数据路径（38）进行同步数据传输的延迟数据使能信号的用于由高频时钟信号（CLK）计时的S-DRAM（1）的延迟时间电路 具有可控等待时间发生器（57），用于以可调延迟时间延迟解码的外部数据使能信号（PAR），比较电路（60）比较高频时钟的周期时间（tcycle） 信号（CLK），具有所述数据路径（38）的预定信号延迟时间，并且如果所述数据路径（38）的信号延迟时间大于所述延迟时间，则将所述等待时间发生器（57）的等待时间缩短循环时间 时钟信号（CLK）的周期时间（tcycle）

公开(公告)号：US07058840B2

公开(公告)日：2006-06-06

申请号：US10143600

申请日：2002-05-10

申请人： Thilo Marx ,  Peter Schrögmeier

发明人： Thilo Marx ,  Peter Schrögmeier

IPC分类号： G06F1/04

CPC分类号： G06F5/06 ,  H03K5/135 ,  H04L7/0008

摘要： An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first signal with the second clock, and second means samples the first signal with a clock phase shifted to the second clock. Means for generating the second signal generates the second signal based on the second clock if it has been determined by at least one means for sampling that the first signal has the predetermined state. Especially for time critical applications, such as a DDR-RAM, a valuable latency saving is provided by the present invention.

公开(公告)号：US07031421B2

公开(公告)日：2006-04-18

申请号：US10135686

申请日：2002-04-30

申请人： Thilo Marx ,  Peter Schrögmeier

发明人： Thilo Marx ,  Peter Schrögmeier

IPC分类号： H03D3/24 ,  H04L7/00

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C7/222 ,  G11C11/4072 ,  G11C19/00

摘要： A Method for initializing an asynchronous latch chain is described, wherein data are taken over through a latch stage at the beginning of the latch chain upon a request signal, the method comprising starting of a clock creation means, like for example a DLL (DLL=delay locket loop), for creating an internal clock on the basis of an external clock, resetting the asynchronous latch chain and applying a start signal to a request signal generation circuit whereupon the creation of a first request signal is enabled on the basis of the internal clock after the clock creation means is settled and after the asynchronous latch chain is reset.

摘要翻译： 描述了一种用于初始化异步锁存器链的方法，其中数据通过在锁存链的开始处的请求信号上的锁存级占用，该方法包括启动时钟创建装置，例如DLL（DLL = 延迟锁定环），用于基于外部时钟创建内部时钟，复位异步锁存链，并将起始信号施加到请求信号生成电路，由此基于内部信号启用第一请求信号的创建 时钟创建装置之后的时钟被置位并且在异步锁存链被复位之后。

公开(公告)号：US06687669B1

公开(公告)日：2004-02-03

申请号：US09214910

申请日：1999-11-03

申请人： Peter Schrögmeier ,  Tim Haulick ,  Klaus Linhard

发明人： Peter Schrögmeier ,  Tim Haulick ,  Klaus Linhard

IPC分类号： G10L2102

CPC分类号： G10L21/0208 ,  G10L21/0264

摘要： In a method for reducing interferences in a voice signal, a noise reduction method is applied to the voice signal, and spectral psychoacoustic masking is taken into account. A spectral masking curve is determined both for the input signal and the output signal of the noise reduction method. By comparing the signal portions exceeding the respective masking curve, newly-audible portions are detected in the form of interference in the output signal and subsequently damped selectively.

摘要翻译： 在减少语音信号干扰的方法中，将噪声降低方法应用于语音信号，并考虑频谱心理声学掩蔽。 确定噪声降低方法的输入信号和输出信号的频谱掩蔽曲线。 通过比较超过相应屏蔽曲线的信号部分，以可能的形式在输出信号中检测新的可听见的部分，然后选择性地衰减。