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12 条记录 (耗时 0.022 秒)

    Latency time switch for an S-DRAM
    1.
    发明授权
    Latency time switch for an S-DRAM 失效
    S-DRAM的延迟时间切换

    公开(公告)号：US06804165B2

    公开(公告)日：2004-10-12

    申请号：US10374657

    申请日：2003-02-26

    申请人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Kieser ,  Pramod Acharya

    发明人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Kieser ,  Pramod Acharya

    IPC分类号： G11C800

    CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

    摘要： Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)

    摘要翻译： 用于产生用于通过S-DRAM的数据路径（38）进行同步数据传输的延迟数据使能信号的用于由高频时钟信号（CLK）计时的S-DRAM（1）的延迟时间电路 具有可控等待时间发生器（57），用于以可调延迟时间延迟解码的外部数据使能信号（PAR），比较电路（60）比较高频时钟的周期时间（tcycle） 信号（CLK），具有所述数据路径（38）的预定信号延迟时间，并且如果所述数据路径（38）的信号延迟时间大于所述延迟时间，则将所述等待时间发生器（57）的等待时间缩短循环时间 时钟信号（CLK）的周期时间（tcycle）

    DDR memory and storage method
    2.
    发明授权
    DDR memory and storage method 有权
    DDR内存和存储方式

    公开(公告)号：US06731567B2

    公开(公告)日：2004-05-04

    申请号：US10350482

    申请日：2003-01-24

    申请人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

    发明人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C11/4093 ,  G11C2207/107

    摘要： The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the data clock signal, and a serial-parallel converter is used to put together a prescribed number of data items from the data read in to give a prescribed number of words from data words having the prescribed word length. To make transferring the data from one synchronization area to another synchronization area, and resynchronization thereof, more reliable, the invention involves an interface memory copying the at least one data word from the serial-parallel converter upon receipt of a copy signal which is synchronous with the data block signal and outputting it to a bus upon receipt of an output signal which is synchronous with the system clock signal.

    摘要翻译： 本发明涉及DDR存储器和存储方法，用于将数据存储在具有多个存储单元的DDR存储器中，每个存储器单元具有规定的字长，其中使用串行数据输入来读取串行数据上升或 数据时钟信号的下降沿和串行 - 并行转换器用于将从读取的数据中的规定数量的数据项组合在一起，以从具有规定字长的数据字中给出规定数量的字。为了传送 数据从一个同步区域到另一个同步区域，并且其再同步更可靠，本发明涉及一种接收存储器，该接口存储器在接收到与数据块信号同步的复制信号时从串行 - 并行转换器复制至少一个数据字 并在接收到与系统时钟信号同步的输出信号时将其输出到总线。

    Latency time circuit for an S-DRAM
    3.
    发明授权
    Latency time circuit for an S-DRAM 失效
    S-DRAM的延迟时间电路

    公开(公告)号：US06819624B2

    公开(公告)日：2004-11-16

    申请号：US10249029

    申请日：2003-03-11

    申请人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

    发明人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

    IPC分类号： G11C800

    CPC分类号： G11C7/222 ,  G11C7/1072 ,  H03L7/0814

    摘要： Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

    摘要翻译： S-DRAM的延迟时间电路，其由高频时钟信号计时，用于产生用于通过S-DRAM的数据路径进行同步数据传输的延迟数据使能控制信号，具有至少一个可控延迟时间发生器，用于 延迟具有可调延迟时间的解码数据使能控制信号，其特征在于至少一个比较电路，该比较电路将高频时钟信号的周期时间与预定的解码时间进行比较，以及通过信号延迟电路可以被接通 比较电路的装置，以便在预定的延迟时间延迟解码的数据使能控制信号，其中当时钟信号的周期时间处于限制时间区域时，信号延迟电路被比较电路接通 位于预定的解码时间。

    Circuit configuration with a memory array
    5.
    发明授权
    Circuit configuration with a memory array 有权

    公开(公告)号：US06614700B2

    公开(公告)日：2003-09-02

    申请号：US10116826

    申请日：2002-04-05

    申请人： Stefan Dietrich ,  Peter Schrögmeier ,  Sabine Kieser ,  Christian Weis

    发明人： Stefan Dietrich ,  Peter Schrögmeier ,  Sabine Kieser ,  Christian Weis

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/22

    摘要： The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

    Integrated memory, and a method of operating an integrated memory
    7.
    发明授权
    Integrated memory, and a method of operating an integrated memory 失效
    集成存储器以及操作集成存储器的方法

    公开(公告)号：US06882554B2

    公开(公告)日：2005-04-19

    申请号：US10287501

    申请日：2002-11-04

    申请人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    发明人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    IPC分类号： G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06

    CPC分类号： G11C7/067 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/105

    摘要： An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

    摘要翻译： 集成存储器具有用于激活读/写放大器的行线，列线和列选择线。 在每种情况下，一组预定数量的存储单元属于行和列地址。 此外，存储器具有对应于预定数量的多个连接焊盘。 一组存储器单元中的每个存储器单元与一个连接焊盘相关联。 设计用于控制存储器访问的控制电路，并且可以操作该控制电路，使得通过列地址激活至少两个不同的列选择线。 对于两个或更多列地址，其中一列列选择行被激活。 因此，可以减小存储芯片上的延迟时间和线路长度。

    Control circuit for an S-DRAM
    8.
    发明授权
    Control circuit for an S-DRAM 有权
    用于S-DRAM的控制电路

    公开(公告)号：US06717886B2

    公开(公告)日：2004-04-06

    申请号：US10248874

    申请日：2003-02-26

    申请人： Acharya Pramod ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier ,  Christian Weis

    发明人： Acharya Pramod ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/4076

    摘要： Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.

    摘要翻译： 用于由具有用于存储等待时间值的可编程模式寄存器的由高频时钟信号计时的S-DRAM的数据路径的控制电路; 延迟发生器，用于以可切换的等待时间延迟由内部序列控制器产生的数据路径控制信号; 延迟解码器，其以取决于存储在模式寄存器中的等待时间值的方式切换等待时间发生器，由至少一个信号延迟元件提供，其可由等待时间解码器切换并用于信号延迟 具有特定延迟时间的数据路径控制信号，如果存储的等待时间值高，延迟解码器切换相关联的信号延迟元件。