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92 条记录 (耗时 0.046 秒)

    Method and circuit arrangement for resetting an integrated circuit
    1.
    发明授权
    Method and circuit arrangement for resetting an integrated circuit 有权
    用于复位集成电路的方法和电路装置

    公开(公告)号：US07363561B2

    公开(公告)日：2008-04-22

    申请号：US11117736

    申请日：2005-04-29

    申请人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrögmeier

    发明人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrögmeier

    IPC分类号： G01R31/28

    CPC分类号： G06F1/24 ,  H03K5/1534

    摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

    摘要翻译： 本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路 电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。 本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

    Integrated memory having column decoder for addressing corresponding bit line
    5.
    发明授权
    Integrated memory having column decoder for addressing corresponding bit line 失效
    具有用于寻址相应位线的列解码器的集成存储器

    公开(公告)号：US06188642B1

    公开(公告)日：2001-02-13

    申请号：US09348736

    申请日：1999-07-06

    申请人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    发明人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    IPC分类号： G11C800

    CPC分类号： G11C8/00

    摘要： The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.

    摘要翻译： 集成存储器具有用于解码列地址并用于寻址对应位线的列解码器。 存储器还具有第一列地址总线，其用于将第一列地址传送到列解码器，以及第二列地址总线，其用于将第二列地址传送到列解码器。 列解码器在每种情况下都对应于提供给它的第一列地址和第二列地址的位线。

    Integrated memory, and a method of operating an integrated memory
    6.
    发明授权
    Integrated memory, and a method of operating an integrated memory 失效
    集成存储器以及操作集成存储器的方法

    公开(公告)号：US06882554B2

    公开(公告)日：2005-04-19

    申请号：US10287501

    申请日：2002-11-04

    申请人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    发明人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    IPC分类号： G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06

    CPC分类号： G11C7/067 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/105

    摘要： An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

    摘要翻译： 集成存储器具有用于激活读/写放大器的行线，列线和列选择线。 在每种情况下，一组预定数量的存储单元属于行和列地址。 此外，存储器具有对应于预定数量的多个连接焊盘。 一组存储器单元中的每个存储器单元与一个连接焊盘相关联。 设计用于控制存储器访问的控制电路，并且可以操作该控制电路，使得通过列地址激活至少两个不同的列选择线。 对于两个或更多列地址，其中一列列选择行被激活。 因此，可以减小存储芯片上的延迟时间和线路长度。

    Integrated circuit and method for testing it
    7.
    发明授权
    Integrated circuit and method for testing it 有权
    集成电路及其测试方法

    公开(公告)号：US06401224B1

    公开(公告)日：2002-06-04

    申请号：US09261100

    申请日：1999-03-02

    申请人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich

    发明人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich

    IPC分类号： G01R3128

    CPC分类号： G01R31/3185

    摘要： A test method suitable for testing at least one integrated circuit which, on a main area, has contact areas that serve to transfer signals during a first operating mode of the circuit. Only some of the contact areas are contact-connected to test contacts of a test apparatus and the circuit is put into a second operating mode in which the signals which are transferred via at least one of the non-contact-connected contact areas in the first operating mode are transferred via at least one of the contact-connected contact areas.

    摘要翻译： 一种适用于测试至少一个集成电路的测试方法，该集成电路在主区域具有用于在电路的第一操作模式期间传送信号的接触区域。 只有一些接触区域接触连接到测试装置的测试触点，并且电路进入第二操作模式，其中通过第一操作模式中的至少一个非接触连接的接触区域传送的信号 操作模式通过至少一个接触连接的接触区域传送。

    Read latency control circuit
    10.
    发明申请
    Read latency control circuit 有权
    读延迟控制电路

    公开(公告)号：US20050270852A1

    公开(公告)日：2005-12-08

    申请号：US11136712

    申请日：2005-05-25

    申请人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schroegmeier

    发明人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schroegmeier

    IPC分类号： G06F3/06 ,  G11C7/22 ,  G11C11/4076

    CPC分类号： G11C11/4076 ,  G11C7/1066 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C2207/2272

    摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.

    摘要翻译： 本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。 本发明还提供了一种用于执行该方法的相应电路装置。