公开(公告)号：US20200159679A1

公开(公告)日：2020-05-21

申请号：US16752612

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. KACHARE ,  Fred WORLEY ,  Harry ROGERS ,  Wentao WU ,  Nagarajan SUBRAMANIYAN

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

公开(公告)号：US20190310956A1

公开(公告)日：2019-10-10

申请号：US16207080

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul OLARIG ,  Fred WORLEY ,  Oscar P. PINTO

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

Abstract: A Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic is disclosed. The PCIe switch may include an external connector to enable the PCIe switch to communicate with a processor and at least one connector to enable the PCIe switch to communicate with at least one storage device. The PCIe switch may include a Power Processing Unit (PPU) to handle configuration of the PCIe switch. The Erasure Coding logic may include an Erasure Coding Controller with circuitry to apply an Erasure Coding scheme to data stored on the storage device, and a snooping logic including circuitry to intercept a data transmission received at the PCIe switch and modify the data transmission responsive to the Erasure Coding scheme.

公开(公告)号：US20190272250A1

公开(公告)日：2019-09-05

申请号：US16124182

申请日：2018-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. KACHARE ,  Stephen FISCHER ,  Fred WORLEY ,  Sompong Paul OLARIG

IPC: G06F13/42 ,  G06F9/445 ,  G06F13/16

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream endpoint enables communication with the processor; two downstream root ports enable communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include two endpoints of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

公开(公告)号：US20250103532A1

公开(公告)日：2025-03-27

申请号：US18959586

申请日：2024-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul OLARIG ,  Fred WORLEY ,  Son PHAM

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

Abstract: A system includes a fabric switch including a motherboard, a baseboard management controller (BMC), a network switch configured to transport network signals, and a PCIe switch configured to transport PCIe signals; a midplane; and a plurality of device ports. Each of the plurality of device ports is configured to connect a storage device to the motherboard of the fabric switch over the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable in multiple modes based a protocol established over a fabric connection between the system and the storage device.

公开(公告)号：US20240095196A1

公开(公告)日：2024-03-21

申请号：US18513610

申请日：2023-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul OLARIG ,  Fred WORLEY ,  Oscar P. PINTO

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/40 ,  G06F13/42 ,  H03M13/15

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0683 ,  G06F13/4022 ,  G06F13/4282 ,  H03M13/154 ,  G06F2213/0026

Abstract: A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD), a Field Programmable Gate Array (FPGA) to implement one or more functions supporting the NVMe SSD, such as data acceleration, data deduplication, data integrity, data encryption, and data compression, and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may communicate with both the FPGA and the NVMe SSD.

公开(公告)号：US20210182221A1

公开(公告)日：2021-06-17

申请号：US17187735

申请日：2021-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. KACHARE ,  Fred WORLEY ,  Harry ROGERS ,  Wentao WU ,  Nagarajan SUBRAMANIYAN

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A system is disclosed. An upstream interface enables communication with a processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for data, and a storage device acceleration module to assist the acceleration module in executing the acceleration instruction.

公开(公告)号：US20200334190A1

公开(公告)日：2020-10-22

申请号：US16921923

申请日：2020-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul OLARIG ,  Son T. PHAM ,  Fred WORLEY

IPC: G06F13/42 ,  G06F13/38

Abstract: A device may include a connector to connect the device to a chassis. The device may include chassis type circuitry to determine a type of the chassis. The device may further include mode configuration circuitry to configure the device to use a particular mode appropriate for the type of the chassis.

公开(公告)号：US20200019336A1

公开(公告)日：2020-01-16

申请号：US16140521

申请日：2018-09-24

Applicant: Samsung Electronics Co., Ltd. ,  Stellus Technologies, Inc.

Inventor： Ramdas P. KACHARE ,  Fred WORLEY ,  Abhijit APHALE

IPC: G06F3/06 ,  G06F11/34

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to facilitate communication of memory accesses, for a storage memory, between the apparatus and a host device. The apparatus may include a statistics monitor circuit configured to record, as the memory accesses occur, statistics regarding data associated with the memory accesses. The apparatus may include a memory interface circuit configured to communicate the memory accesses between the apparatus and at least one storage memory.

公开(公告)号：US20190272245A1

公开(公告)日：2019-09-05

申请号：US15981801

申请日：2018-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul OLARIG ,  Fred WORLEY

IPC: G06F13/40 ,  G06F13/16

Abstract: A rack-mountable data storage system includes: a chassis including one or more switchboards; a midplane interfacing with the one or more switchboards; and one or more data storage devices removably coupled to the midplane using a connector. At least one data storage device of the one or more data storage devices include a logic device to interface with the midplane. The logic device provides a device-specific interface of a corresponding data storage device with the midplane. The at least one data storage device is configured using the logic device according to a first protocol based on a signal on a pin of the connector, and the at least one data storage device is reconfigurable according to a second protocol based on a change of the signal on the pin of the connector using the logic device.

公开(公告)号：US20190272241A1

公开(公告)日：2019-09-05

申请号：US16124179

申请日：2018-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. KACHARE ,  Fred WORLEY ,  Harry ROGERS ,  Wentao WU ,  Nagarajan SUBRAMANIYAN

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a physical function (PF) to expose the storage device, a second function to expose the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. A downstream filter associated with the downstream port may intercept an acceleration instruction associated with a downstream Filter Address Range (FAR) received from the storage device and deliver the acceleration instruction to the APM-F, the acceleration instruction being. An upstream filter associated with the upstream port may intercept an acceleration instruction received from the processor and deliver the second acceleration instruction to the APM-F. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.