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公开(公告)号：US11069417B2
公开(公告)日：2021-07-20
申请号：US16940935
申请日：2020-07-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeduk Yu , Bongsoon Lim , Yonghyuk Choi
Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.
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22.发明申请公开(公告)号：US20210096967A1
公开(公告)日：2021-04-01
申请号：US16865948
申请日：2020-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Sangwan Nam , Jaeduk Yu , Sangwon Park , Bongsoon Lim
Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.
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公开(公告)号：US20200335169A1
公开(公告)日：2020-10-22
申请号：US16661351
申请日：2019-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeduk Yu , Dongkyo Shim
Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. when the When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.
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24.发明授权公开(公告)号：US12147666B2
公开(公告)日：2024-11-19
申请号：US18052428
申请日：2022-11-03
Applicant: Samsung Electronics Co., Ltd.
IPC: G06F3/06
Abstract: According to an example embodiment of the inventive concepts, an operating method of a memory system including a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control by the memory controller and the non-volatile memory including a first memory block and a second memory block, the method includes determining, by the memory controller, whether the first memory block satisfies a block reset condition, in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block, transferring data pre-programmed in the first memory block to the second memory block, erasing the first memory block, and re-programming the dummy cells of the first memory block.
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25.发明授权公开(公告)号：US12119046B2
公开(公告)日：2024-10-15
申请号：US18045541
申请日：2022-10-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeduk Yu , Yohan Lee , Yonghyuk Choi , Jiho Cho
IPC: G11C16/34 , G11C11/4074 , G11C11/408 , G11C11/4096
CPC classification number: G11C11/4085 , G11C11/4074 , G11C11/4096
Abstract: A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.
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Patent Agency Ranking
公开(公告)号：US11929118B2
公开(公告)日：2024-03-12
申请号：US17748156
申请日：2022-05-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Yohan Lee , Sangwon Park , Jaeduk Yu
CPC classification number: G11C16/0433 , G11C7/1039 , G11C16/08 , G11C16/102 , G11C16/24 , G11C16/26
Abstract: Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.
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公开(公告)号：US11881272B2
公开(公告)日：2024-01-23
申请号：US18159882
申请日：2023-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Sangwan Nam , Jaeduk Yu , Yohan Lee
IPC: G11C16/04 , G11C16/34 , G11C16/08 , G11C16/10 , G11C16/24 , H01L23/00 , H01L25/065 , H01L25/18 , H10B41/27 , H10B43/27
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511 , H10B41/27 , H10B43/27
Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.
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28.发明授权公开(公告)号：US11797405B2
公开(公告)日：2023-10-24
申请号：US17935502
申请日：2022-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Sangwan Nam , Jaeduk Yu , Sangwon Park , Bongsoon Lim
CPC classification number: G06F11/2094 , G11C16/0483 , G11C16/08 , G06F2201/85 , H10B41/27 , H10B43/27
Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.
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29.发明公开公开(公告)号：US20230140959A1
公开(公告)日：2023-05-11
申请号：US18149206
申请日：2023-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk CHOI , Bongsoon LIM , Hongsoo JEON , Jaeduk Yu
IPC: H01L25/18 , H01L25/065 , H01L23/00 , G11C16/08 , G11C16/04
CPC classification number: H01L25/18 , H01L25/0657 , H01L24/05 , H01L24/08 , G11C16/08 , G11C16/0483 , H01L2924/14511 , H01L2224/05147 , H01L2224/08145 , H01L2924/1431
Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.
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公开(公告)号：US11615855B2
公开(公告)日：2023-03-28
申请号：US17334045
申请日：2021-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Sangwan Nam , Jaeduk Yu , Yohan Lee
IPC: G11C16/04 , G11C16/34 , G11C16/08 , G11C16/10 , G11C16/24 , H01L23/00 , H01L25/065 , H01L25/18 , H01L27/11556 , H01L27/11582
Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.
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