公开(公告)号：US10790305B2

公开(公告)日：2020-09-29

申请号：US16409129

申请日：2019-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Ji-Su Yu ,  Hyeon-gyu You ,  Seung-Young Lee ,  Jae-Boong Lee ,  Jong-Hoon Jung

IPC: H01L23/52 ,  H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.

公开(公告)号：US20190198491A1

公开(公告)日：2019-06-27

申请号：US16191720

申请日：2018-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho Do ,  Dal-Hee Lee ,  Jin-Young Lim ,  Tae-Joong Song ,  Jong-Hoon Jung

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/768 ,  G11C8/16 ,  G11C11/412

CPC classification number: H01L27/0207 ,  G11C8/16 ,  G11C11/412 ,  H01L21/76895 ,  H01L27/088

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

公开(公告)号：US20180173835A1

公开(公告)日：2018-06-21

申请号：US15689008

申请日：2017-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  Jong-Hoon Jung ,  Seung-Young Lee ,  Tae-Joong Song

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F1/70 ,  G03F7/70283 ,  G03F7/70466 ,  G06F17/5009 ,  G06F17/5068 ,  G06F17/5081

Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.

公开(公告)号：US09940998B2

公开(公告)日：2018-04-10

申请号：US15469037

申请日：2017-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hoon Jung ,  Sung-Hyun Park ,  Woo-Jin Rim

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/418

Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of complementary bit lines connected to the plurality of memory cells, a plurality of auxiliary bit lines, a plurality of auxiliary complementary bit lines, and a switch circuit. The switch circuit electrically connects the plurality of auxiliary bit lines to the plurality of bit lines during a write operation, electrically connects the plurality of auxiliary complementary bit lines to the plurality of complementary bit lines during the write operation, electrically disconnects the plurality of auxiliary bit lines from the plurality of bit lines during a read operation, and electrically disconnects the plurality of auxiliary complementary bit lines from the plurality of complementary bit lines during the read operation.