公开(公告)号：US09379705B2

公开(公告)日：2016-06-28

申请号：US14624646

申请日：2015-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dal-Hee Lee ,  Jae-Woo Seo ,  Min-Ho Park

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0944 ,  G06F17/50

CPC classification number: H03K19/0013 ,  G06F17/5072 ,  H03K19/018507 ,  H03K19/018521 ,  H03K19/0944

Abstract: An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.

Abstract translation: 集成电路（IC）包括至少一个单元电池。 所述至少一个单元单元包括被配置为处理第一位信号的第一位电路，被配置为处理第二位信号的第二位电路，与所述至少一个单位单元的边界间隔开的第一阱，并被偏置到第一位 电压，第二阱偏压到不同于第一电压的第二电压。 第一和第二位电路中的每一个包括设置在第一阱中的多个晶体管中的至少一个晶体管。

公开(公告)号：US11955471B2

公开(公告)日：2024-04-09

申请号：US17584930

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho Do ,  Dal-Hee Lee ,  Jin-Young Lim ,  Tae-Joong Song ,  Jong-Hoon Jung

IPC: H01L27/02 ,  G06F30/00 ,  G11C5/06 ,  G11C8/16 ,  G11C11/412 ,  H01L21/768 ,  H01L27/088 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F30/00 ,  G11C5/063 ,  G11C8/16 ,  G11C11/412 ,  H01L21/76895 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11875

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

公开(公告)号：US09960768B2

公开(公告)日：2018-05-01

申请号：US15178154

申请日：2016-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dal-Hee Lee ,  Jae-Woo Seo ,  Min-Ho Park

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0944 ,  G06F17/50

CPC classification number: H03K19/0013 ,  G06F17/5072 ,  H03K19/018507 ,  H03K19/018521 ,  H03K19/0944

Abstract: An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.

公开(公告)号：US11335673B2

公开(公告)日：2022-05-17

申请号：US16191720

申请日：2018-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho Do ,  Dal-Hee Lee ,  Jin-Young Lim ,  Tae-Joong Song ,  Jong-Hoon Jung

IPC: H01L27/02 ,  H01L27/118 ,  G11C5/06 ,  G06F30/00 ,  G11C8/16 ,  G11C11/412 ,  H01L21/768 ,  H01L27/088

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

公开(公告)号：US11287474B2

公开(公告)日：2022-03-29

申请号：US16552109

申请日：2019-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Sung-We Cho ,  Dal-Hee Lee ,  Jae-Ha Lee

IPC: G01R31/3185 ,  H03K3/3562

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

公开(公告)号：US10429443B2

公开(公告)日：2019-10-01

申请号：US15663852

申请日：2017-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Sung-Wee Cho ,  Dal-Hee Lee ,  Jae-Ha Lee

IPC: G01R31/3185 ,  H03K3/3562

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

公开(公告)号：US20220149032A1

公开(公告)日：2022-05-12

申请号：US17584930

申请日：2022-01-26

Applicant: Samsung Electronics, Co., Ltd.

Inventor： Jung-Ho Do ,  Dal-Hee Lee ,  Jin-Young Lim ,  Tae-Joong Song ,  Jong-Hoon Jung

IPC: H01L27/02 ,  H01L27/118 ,  G11C5/06 ,  G06F30/00 ,  G11C8/16 ,  G11C11/412 ,  H01L21/768 ,  H01L27/088

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

公开(公告)号：US20190198491A1

公开(公告)日：2019-06-27

申请号：US16191720

申请日：2018-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho Do ,  Dal-Hee Lee ,  Jin-Young Lim ,  Tae-Joong Song ,  Jong-Hoon Jung

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/768 ,  G11C8/16 ,  G11C11/412

CPC classification number: H01L27/0207 ,  G11C8/16 ,  G11C11/412 ,  H01L21/76895 ,  H01L27/088

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

公开(公告)号：US09831877B2

公开(公告)日：2017-11-28

申请号：US15211468

申请日：2016-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dal-Hee Lee ,  Jae-Woo Seo

IPC: H03K19/0185 ,  H01L27/092 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H03K19/0013

Abstract: An integrated circuit (IC) includes a first circuit, a first well and a second circuit. The first circuit is disposed on a substrate and configured to shift a first bit signal between a first voltage logic level and a second logic voltage level. The first well is disposed in a cell on the substrate and biased to a first voltage. The first well is spaced apart from a first edge of the cell. The second well is disposed in the cell and biased to a second voltage. The second well is disposed to contact a second edge of the cell opposite to the first edge. The first circuit includes a plurality of transistors respectively disposed in the first and second wells.

公开(公告)号：US08952423B2

公开(公告)日：2015-02-10

申请号：US13785156

申请日：2013-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joong-Won Jeon ,  Hee-Sung Kang ,  Dae-Ho Yoon ,  Dal-Hee Lee ,  Suk-Joo Lee

IPC: H01L27/02 ,  H01L29/94

CPC classification number: H01L27/0207 ,  H01L29/94

Abstract: A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.

Abstract translation: 半导体器件包括布置在半导体器件的中心区域中的逻辑区域和设置在其外部区域中的周边区域。 逻辑区域包括线形逻辑晶体管和盒形去耦电容器。 周边区域包括线形外围晶体管和与外围晶体管相邻设置的线状外围虚拟晶体管。