公开(公告)号：US11792982B2

公开(公告)日：2023-10-17

申请号：US17026377

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Hojun Seong ,  Joonhee Lee ,  Joon-Sung Lim ,  Euntaek Jung

IPC: H01L27/11582 ,  H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

公开(公告)号：US11715712B2

公开(公告)日：2023-08-01

申请号：US17323076

申请日：2021-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Ji Won Kim ,  Jae Ho Ahn ,  Joon-Sung Lim ,  Suk Kang Sung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L23/562 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/3511

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

公开(公告)号：US11315947B2

公开(公告)日：2022-04-26

申请号：US16890115

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho Ahn ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Bum Kyu Kang ,  Sang Don Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556

Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

公开(公告)号：US11127679B2

公开(公告)日：2021-09-21

申请号：US17060142

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Gn Yun ,  Jaesun Yun ,  Joon-Sung Lim

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L27/06 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.

公开(公告)号：US11024640B2

公开(公告)日：2021-06-01

申请号：US16514557

申请日：2019-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Jiyoung Kim ,  Jiwon Kim ,  Woosung Yang

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11551 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11565

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern.

公开(公告)号：US11011543B2

公开(公告)日：2021-05-18

申请号：US16889947

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Sung Lim ,  Jang-Gn YuN ,  Jaesun Yun

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor pattern.

公开(公告)号：US10804363B2

公开(公告)日：2020-10-13

申请号：US16445815

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Jiyoung Kim ,  Jiwon Kim ,  Woosung Yang

IPC: H01L29/417 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device comprises a substrate that includes a cell array region and a connection region, an electrode structure that includes a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate and has a stepwise structure on the connection region, an etch stop pattern that covers the stepwise structure of the electrode structure. The electrode structure and the etch stop pattern extend in a first direction when viewed in plan. The electrode structure has a first width in a second direction intersecting the first direction. The etch stop pattern has a second width in the second direction. The second width is less than the first direction.

公开(公告)号：US10431593B2

公开(公告)日：2019-10-01

申请号：US15860082

申请日：2018-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Kyoil Koo ,  Hoosung Cho ,  Sunyoung Kim ,  Cheol Ryou ,  Jaesun Yun

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/1157

Abstract: Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.

公开(公告)号：US10403634B2

公开(公告)日：2019-09-03

申请号：US15989477

申请日：2018-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Gilsung Lee ,  Eunsuk Cho

IPC: H01L27/11573 ,  G11C16/24 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.

公开(公告)号：US10332900B2

公开(公告)日：2019-06-25

申请号：US15801551

申请日：2017-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-Ok Yun ,  Jang-Gn Yun ,  Joon-Sung Lim ,  Sung-Min Hwang

IPC: H01L21/28 ,  H01L27/115 ,  H01L23/522 ,  H01L23/535 ,  H01L29/423 ,  H01L29/49 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575

Abstract: A vertical memory device includes a gate structure on a peripheral circuit region of a substrate, the substrate including a cell region and the peripheral circuit region, and the gate structure including a first gate electrode, second, third, and fourth gate electrodes sequentially disposed at a plurality of levels, respectively, on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a first epitaxial layer extending through the second gate electrode on the cell region of the substrate, a channel extending through the third and fourth gate electrodes in the vertical direction on the first epitaxial layer, and a second epitaxial layer on a portion of the peripheral circuit region of the substrate adjacent the gate structure.