公开(公告)号：US20240330038A1

公开(公告)日：2024-10-03

申请号：US18595994

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin KIM ,  Jimin Lee ,  Junho Huh

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F9/4818 ,  G06F9/30101 ,  G06F9/461

Abstract: The present disclosure provides methods and apparatuses for interrupt processing. An interrupt processing method includes executing a first interrupt by using a common register, receiving a second interrupt and a second priority of the second interrupt during execution of the first interrupt, comparing a first priority of the first interrupt with the second priority of the second interrupt, generating a first register index corresponding to the second priority of the second interrupt by using a look-up table based on the second priority of the second interrupt being greater than the first priority, and, based on the first register index being a dedicated index, maintaining a context of the first interrupt stored in the common register, assigning a dedicated register for execution of the second interrupt, and executing an interrupt program corresponding to the second interrupt by using the assigned dedicated register. The interrupt program is saved in a memory.

公开(公告)号：US20240290738A1

公开(公告)日：2024-08-29

申请号：US18510967

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongwee Yu ,  Junho Huh

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L2224/061 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first die having a first and second physical layer regions adjacent each other, connecting pads and a connecting wire on a lower surface of the first die, a rear wiring layer having a first rear wire on the first die, and through silicon vias penetrating the first die, the through silicon vias including a first and second through silicon vias. The connecting pads include a first and a second connecting pads electrically connected with the first and second physical layer regions respectively, and a first and a second pads electrically connected with the first and second through silicon vias respectively. The first rear wire is electrically connected with the first and second through silicon vias. The connecting wire is electrically connected with the first connecting pad and the first pad.

公开(公告)号：US11722316B2

公开(公告)日：2023-08-08

申请号：US16923521

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younsung Chu ,  Junho Huh

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/00

CPC classification number: H04L9/3263 ,  H04L9/0643 ,  H04L9/3236 ,  H04L9/3247 ,  H04L9/50

Abstract: A cryptographic communication system includes an electronic device configured to output a certificate and a transaction including a first hash value in which a certificate is hashed certificate, and a node configured to first determine whether the electronic device generated the transaction based on the transaction and the certificate, to second determine whether information included in the transaction and information included in the certificate coincide, and to third add a block to a distributed ledger depending on the result of the first determining and the second determining. The block includes the transaction, and the electronic device is configured to generate the certificate such that the certificate includes an ID of the electronic device and a public key of the electronic device.

公开(公告)号：US11551699B2

公开(公告)日：2023-01-10

申请号：US17052736

申请日：2019-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junho Huh ,  Hyoungshik Kim ,  Muhammad Ejaz Ahmed ,  Ilyoup Kwak ,  Iljoo Kim ,  Sangjoon Je

IPC: G10L17/22 ,  G06F21/32 ,  G06F21/45 ,  G10L17/02 ,  G10L17/04 ,  G10L17/06 ,  G10L25/21

Abstract: Provided are a method of authenticating a voice input provided from a user and a method of detecting a voice input having a strong attack tendency. The voice input authentication method includes: receiving the voice input; obtaining, from the voice input, signal characteristic data representing signal characteristics of the voice input; and authenticating the voice input by applying the obtained signal characteristic data to a first learning model configured to determine an attribute of the voice input, wherein the first learning model is trained to determine the attribute of the voice input based on a voice uttered by a person and a voice output by an apparatus.

公开(公告)号：US11550906B2

公开(公告)日：2023-01-10

申请号：US16790217

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghyun Kim ,  Yoonjick Lee ,  Junho Huh

IPC: G06F21/55 ,  G06F3/06 ,  G06F21/62 ,  G06F12/14

Abstract: A storage system includes a host device including a host processor and a secure element distinguished from the host processor, and a storage device that includes a first memory area accessed by the host processor, and a second memory area distinguished from the first memory area and accessed by the secure element. The host processor includes a first replay protected memory block (RPMB) key and a first RPMB counter for a first RPMB subsystem of the host processor. The secure element includes a second RPMB key and a second RPMB counter for a second RPMB subsystem of secure element. The first memory area includes a third RPMB key, a third RPMB counter and a first data space of the first RPMB sub-system. The second memory area includes a fourth RPMB key, a fourth RPMB counter and a second data space of the second RPMB sub-system.

公开(公告)号：US20230004210A1

公开(公告)日：2023-01-05

申请号：US17943857

申请日：2022-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungchul JEON ,  Jae Min Kim ,  Hyunseok Kim ,  Junho Huh

IPC: G06F1/3287 ,  G06F1/3296 ,  H03K17/687

Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

公开(公告)号：US11176259B2

公开(公告)日：2021-11-16

申请号：US16357841

申请日：2019-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Min Kim ,  Jae Won Lee ,  Junho Huh

IPC: G06F21/60 ,  G06F16/182 ,  H04L9/08 ,  H04L9/32 ,  H04L9/06

Abstract: An electronic system includes a plurality of hardware devices and an authenticated circuit. The authenticated circuit is integrated, as fixed hardware, in the electronic system together with the plurality of hardware devices during a manufacturing process of the electronic system, the authenticated circuit configured to verify system integrity based on a system identification code provided from inside of the electronic system by at least one of the plurality of hardware devices, the system integrity indicating that a combination of the authenticated circuit and the plurality of hardware devices has not been modified since the manufacturing process, the authenticated circuit configured to perform a mining operation to generate a next block, the next block to be linked to a blockchain only in response to the authenticated circuit verifying the system integrity. Indiscriminate mining competition may be prevented or reduced in likelihood of occurrence.

公开(公告)号：US11039005B2

公开(公告)日：2021-06-15

申请号：US16719330

申请日：2019-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Junho Huh ,  Ilyoup Kwak ,  Hyoungshick Kim ,  Woojin Park

IPC: H04M1/72457 ,  H04W4/021 ,  H04W4/02 ,  H04W48/04 ,  H04W12/08 ,  H04B17/318 ,  H04M1/72454 ,  H04W12/37 ,  H04W12/63

Abstract: Disclosed are a location-based operation method, an electronic device, and a recording medium. The electronic device may include a memory storing instructions; and a processor configured to execute the instructions to: identify a first location of the electronic device based on first communication information; obtain, based on the identified first location being identified as being included in a second location area that is adjacent to and includes a first location area, second communication information; identify a second location of the electronic device based on at least a part of the obtained second communication information; and change a locked state of the electronic device to an unlocked state, based on the second location of the electronic device being identified as being included in the first location area.

公开(公告)号：US20210042157A1

公开(公告)日：2021-02-11

申请号：US16789602

申请日：2020-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemin Kim ,  Byungchul Jeon ,  Junho Huh

IPC: G06F9/48 ,  G06F11/30 ,  G06F11/34 ,  G06F1/3287 ,  G06F9/50

Abstract: In a method of operating a multi-core system comprising a plurality of processor cores, a plurality of task stall information respectively corresponding to a plurality of tasks are provided by monitoring a task stall time with respect to each task. The task stall time indicates a time while the each task is suspended within a task active time, and the task active time indicates a time while a corresponding processor core is occupied by the each task. Task scheduling is performed based on the plurality of task stall information, and a fine-grained dynamic voltage and frequency scaling (DVFS) is performed based on the task scheduling. The plurality of tasks may be assigned to the plurality of processor cores based on load unbalancing, and the effects of the fine-grained DVFS may be increased to reduce the power consumption of the multi-core system.