公开(公告)号：US11658075B2

公开(公告)日：2023-05-23

申请号：US17246778

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmin Yoo ,  Juyoun Kim ,  Hyungjoo Na ,  Bongseok Suh ,  Jooho Jung ,  Euichul Hwang ,  Sungmoon Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/118 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L27/11807 ,  H01L2027/11816 ,  H01L2027/11829 ,  H01L2027/11861

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US11600694B2

公开(公告)日：2023-03-07

申请号：US17106971

申请日：2020-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim

IPC: H01L29/06 ,  H01L27/11

Abstract: An integrated circuit device includes an active area extending in a first direction on a substrate and a gate line extending in a second direction intersecting with the first direction to intersect with the active area. The gate line comprises a first sidewall and a second sidewall opposite to each other. The first sidewall has a convex shape. The second sidewall has a concave shape.

公开(公告)号：US11575018B2

公开(公告)日：2023-02-07

申请号：US17153464

申请日：2021-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Junmo Park ,  Seulgi Yun

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor memory device includes a substrate having a first region and a second region. A first gate electrode layer is on the first region and includes a first conductive layer including a first plurality of layers, and includes a first upper conductive layer on the first conductive layer. A second gate electrode layer is on the second region and includes a second conductive layer including a second plurality of layers, and includes a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes titanium oxynitride (TiON). A first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are metal oxide semiconductor field effect transistors (MOSFETs) having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

公开(公告)号：US20210328038A1

公开(公告)日：2021-10-21

申请号：US17153464

申请日：2021-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Junmo Park ,  Seulgi Yun

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor memory device includes a substrate having a first region and a second region. A first gate electrode layer is on the first region and includes a first conductive layer including a first plurality of layers, and includes a first upper conductive layer on the first conductive layer. A second gate electrode layer is on the second region and includes a second conductive layer including a second plurality of layers, and includes a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes titanium oxynitride (TiON). A first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are metal oxide semiconductor field effect transistors (MOSFETs) having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

公开(公告)号：US11043430B2

公开(公告)日：2021-06-22

申请号：US16921037

申请日：2020-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/51 ,  H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US09293701B2

公开(公告)日：2016-03-22

申请号：US14527176

申请日：2014-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Juyoun Kim ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.

Abstract translation: 可变电阻存储器件包括栅极图案和设置在基板上相同电平上的虚拟栅极图案，设置在伪栅极图案上的第一接触图案和设置在伪栅极图案和第一接触图案之间的可变电阻图案 。 栅极图案和虚拟栅极图案分别限定功能和非功能晶体管的导电电极。 第一接触图案和伪栅极图案分别限定可变电阻图案上的上电极和下电极。 还讨论了相关的制造方法。

公开(公告)号：US20150144862A1

公开(公告)日：2015-05-28

申请号：US14527176

申请日：2014-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Juyoun Kim ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.

Abstract translation: 可变电阻存储器件包括栅极图案和设置在基板上相同电平上的虚拟栅极图案，设置在伪栅极图案上的第一接触图案和设置在伪栅极图案和第一接触图案之间的可变电阻图案 。 栅极图案和虚拟栅极图案分别限定功能和非功能晶体管的导电电极。 第一接触图案和伪栅极图案分别限定可变电阻图案上的上电极和下电极。 还讨论了相关的制造方法。