公开(公告)号：US20240170546A1

公开(公告)日：2024-05-23

申请号：US18216640

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongheum CHOI ,  Chunghwan SHIN ,  Rakhwan Kim ,  Yeji Song

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41791 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/66795

Abstract: A semiconductor device includes: an active fin disposed on a substrate and protruding from an upper surface of the substrate; a gate structure disposed on the active fin; a source/drain layer disposed on a portion of the active fin adjacent to the gate structure; an ohmic contact pattern on the source/drain layer; and a contact plug disposed on an upper surface of the ohmic contact pattern, wherein the contact plug includes: a conductive structure including a metal; and a barrier pattern covering a lower surface and a sidewall of the conductive structure, wherein a thickness of the barrier pattern is equal to or less than about 10 Å, and wherein a maximum diameter of a grain of the metal included in the conductive structure is in a range of about 8 nn to about 15 nm.

公开(公告)号：US11587867B2

公开(公告)日：2023-02-21

申请号：US17235984

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Kyungwook Kim ,  Rakhwan Kim ,  Seungyong Yoo ,  Eun-Ji Jung

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/45

Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.

公开(公告)号：US20220246528A1

公开(公告)日：2022-08-04

申请号：US17451725

申请日：2021-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungyu Choi ,  Seongheum Choi ,  Daeyong Kim ,  Rakhwan Kim

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate; a gate structure extending in a second direction on the substrate, intersecting the active region, and including a gate electrode, source/drain region disposed on the active region on at least one side of the gate structure, a first contact structure connected to the source/drain region; a first gate contact structure disposed on and connected to the gate electrode; a second contact structure disposed on and connected to the first contact structure; and a second gate contact structure disposed on and connected to the first gate contact structure. The second contact structure and/or the second gate contact structure may include an upper metal layer and a metal liner covering a lower surface and side surfaces of the upper metal layer. An external surface of the metal liner may have surface roughness.

公开(公告)号：US11335680B2

公开(公告)日：2022-05-17

申请号：US16912427

申请日：2020-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

公开(公告)号：US11270944B2

公开(公告)日：2022-03-08

申请号：US16940933

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Rakhwan Kim ,  Eun-Ji Jung

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/02

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.