公开(公告)号：US20230187493A1

公开(公告)日：2023-06-15

申请号：US18166521

申请日：2023-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L27/088 ,  H01L29/7827 ,  H01L29/66666

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first active region including a first vertical field effect transistor (VFET), a second active region including a second VFET, and a diffusion break between the first active region and the second active region on a substrate. The diffusion break may include first and second isolation layers in the substrate and a diffusion break channel region protruding from a portion of the substrate. The portion of the substrate may be between the first isolation layer and the second isolation layer. In some embodiments, the first and second isolation layers may be adjacent to respective opposing sidewalls of the diffusion break channel region.

公开(公告)号：US11569232B2

公开(公告)日：2023-01-31

申请号：US17152388

申请日：2021-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device having a self-aligned gate structure includes: providing at least one channel structure above at least one substrate; depositing at least one gate masking layer on the at least one channel structure so that the at least one gate masking layer is formed on top and side surfaces of the at least one channel structure and spread outward above the at least one substrate to form outer-extended portions of the at least one gate masking layer, before a gate-cut process is performed, wherein the at least one gate masking layer is self-aligned with respect to the at least one channel structure by the depositing; and removing the outer-extended portions of the at least one gate masking layer so that the at least one gate masking layer at both sides of the at least one channel structure has a same width.

公开(公告)号：US20220231134A1

公开(公告)日：2022-07-21

申请号：US17325083

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang-ill Seo ,  Daewon Ha ,  Jason Martineau

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8238

Abstract: Presented are structures and methods for forming such structures that allow for electrical or diffusion breaks between transistors of one level of a stacked transistor device, without necessarily requiring that a like electrical or diffusion break exists in another level of the stacked transistor device. Also presented, an electrical break between transistor devices may be formed by providing a channel of a first polarity with a false gate comprising a work-function metal of an opposite polarity.

公开(公告)号：US12243946B2

公开(公告)日：2025-03-04

申请号：US17504755

申请日：2021-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyoung Park ,  Seunghyun Song ,  Byounghak Hong ,  Seungchan Yun

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first channel layer including a first surface, a second channel layer that is spaced apart from the first channel layer in a first direction and includes a second surface, a first gate electrode and a second gate electrode. The first surface and the second surface may be spaced apart from each other in the first direction and may face opposite directions. The first channel layer may be in the first gate electrode, and the first gate electrode may be absent from the first surface of the first channel layer. The second channel layer may be in the second gate electrode, and the second gate electrode may be absent from the second surface of the second channel layer.

公开(公告)号：US12199152B2

公开(公告)日：2025-01-14

申请号：US17325083

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang-ill Seo ,  Daewon Ha ,  Jason Martineau

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/49

Abstract: Presented are structures and methods for forming such structures that allow for electrical or diffusion breaks between transistors of one level of a stacked transistor device, without necessarily requiring that a like electrical or diffusion break exists in another level of the stacked transistor device. Also presented, an electrical break between transistor devices may be formed by providing a channel of a first polarity with a false gate comprising a work-function metal of an opposite polarity.

公开(公告)号：US12051697B2

公开(公告)日：2024-07-30

申请号：US17361381

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song

IPC: H01L27/092 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/82385 ,  H01L25/074 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate, and the upper transistor may overlap the lower transistor. The upper transistor may include an upper gate structure, and the lower transistor may include a lower gate structure, and the upper gate structure and the lower gate structure may have different widths in a horizontal direction.

公开(公告)号：US20230369317A1

公开(公告)日：2023-11-16

申请号：US18356545

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US11605708B2

公开(公告)日：2023-03-14

申请号：US17094920

申请日：2020-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first active region including a first vertical field effect transistor (VFET), a second active region including a second VFET, and a diffusion break between the first active region and the second active region on a substrate. The diffusion break may include first and second isolation layers in the substrate and a diffusion break channel region protruding from a portion of the substrate. The portion of the substrate may be between the first isolation layer and the second isolation layer. In some embodiments, the first and second isolation layers may be adjacent to respective opposing sidewalls of the diffusion break channel region.

公开(公告)号：US20220336473A1

公开(公告)日：2022-10-20

申请号：US17382060

申请日：2021-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Saehan Park ,  Seungyoung Lee ,  Inchan Hwang

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/762

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

公开(公告)号：US20220302172A1

公开(公告)日：2022-09-22

申请号：US17335834

申请日：2021-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang-ill Seo

IPC: H01L27/12

Abstract: A multi-stack semiconductor device formed to cover a plurality of gate pitches includes: a 1st transistor; a 2nd transistor formed at a right side of the 1st transistor, and isolated from the transistor by a 1st portion of a diffusion break structure; a 3rd transistor formed vertically above or below the 1st transistor; and a 4th transistor formed at a right side of the 3rd transistor, and isolated from the 3rd transistor by a 2nd portion of the diffusion break structure, wherein the 1st portion and the 2nd portion of the diffusion break structure are formed of different material compositions or have different physical dimensions.