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    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES
    22.
    发明申请
    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20140357054A1

    公开(公告)日：2014-12-04

    申请号：US14458998

    申请日：2014-08-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong-Hoon Son ,  Sung-Min Hwang ,  Kihyun Hwang ,  Jaehoon Jang

    IPC: H01L21/762 ,  H01L27/115

    CPC classification number: H01L21/76254 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42348

    Abstract: A semiconductor device can include a first substrate and conductive patterns on the first substrate, where the conductive patterns are disposed in stacks vertically extending from the substrate. An active pillar can be on the first substrate vertically extend from the first substrate throughthe conductive patterns to provide vertical string transistors on the first substrate. A second substrate can be on the conductive patterns and the active pillar opposite the first substrate. A peripheral circuit transistor can be on the second substrate opposite the first substrate, where the peripheral circuit transistor can be adjacent to and overlap an uppermost pattern of the conductive patterns.

    Abstract translation: 半导体器件可以包括第一衬底和第一衬底上的导电图案，其中导电图案布置在从衬底垂直延伸的堆叠中。 活性柱可以在第一衬底上，从第一衬底垂直地延伸穿过导电图案，以在第一衬底上提供垂直串联晶体管。 第二基板可以位于与第一基板相对的导电图案和有源柱上。 外围电路晶体管可以在与第一衬底相对的第二衬底上，其中外围电路晶体管可以与导电图案的最上面的图案相邻并且与其重叠。

    Semiconductor memory devices and methods of fabricating the same
    23.
    发明授权
    Semiconductor memory devices and methods of fabricating the same 有权

    公开(公告)号：US11107828B2

    公开(公告)日：2021-08-31

    申请号：US16902575

    申请日：2020-06-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Eunsuk Cho

    IPC: H01L27/11573 ,  H01L27/1157 ,  H01L25/065 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11575

    Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

    Three-dimensional semiconductor devices including vertical structures with varied spacing
    24.
    发明授权
    Three-dimensional semiconductor devices including vertical structures with varied spacing 有权

    公开(公告)号：US10886296B2

    公开(公告)日：2021-01-05

    申请号：US16563014

    申请日：2019-09-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungjoong Kim ,  Joon-Sung Lim ,  Sung-Min Hwang

    IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11565

    Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.

    Semiconductor memory device and method of manufacturing the same
    25.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权

    公开(公告)号：US10692881B2

    公开(公告)日：2020-06-23

    申请号：US15982213

    申请日：2018-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Jihye Kim

    IPC: H01L27/11582 ,  H01L23/538 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11573

    Abstract: A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.

    Methods of manufacturing a semiconductor device
    30.
    发明授权
    Methods of manufacturing a semiconductor device 有权

    公开(公告)号：US09299716B2

    公开(公告)日：2016-03-29

    申请号：US14790724

    申请日：2015-07-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

    IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66

    CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

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