公开(公告)号：US20240049471A1

公开(公告)日：2024-02-08

申请号：US18322040

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho Kang ,  Seungyeon Kim ,  Jiyoung Kim ,  Woosung Yang ,  Jaeeun Lee ,  Kiwhan Song

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A vertically-integrated nonvolatile memory device includes a peripheral circuit structure with a peripheral circuit therein, and cell array structure that is bonded to the peripheral circuit structure, and has a cell area and a connection area therein. The cell area includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked, in the connection area. The plurality of gate electrodes include a cell stack having a staircase shape, a plurality of capacitor core contact structures configured to pass through the cell stack in the cell area, and a plurality of capacitor gate contact structures connected to the plurality of gate electrodes in the connection area. Each of the plurality of capacitor core contact structures includes: (i) a first core conductor electrically connected to the peripheral circuit, and (ii) a first cover insulating layer extending between the first core conductor and the plurality of gate electrodes, and constitutes a capacitor in which the first core conductor, the first cover insulating layer, and the plurality of gate electrodes are connected to the peripheral circuit.

公开(公告)号：US20240015970A1

公开(公告)日：2024-01-11

申请号：US18372885

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  HOJUN SEONG ,  JOONHEE LEE ,  JOON-SUNG LIM ,  EUNTAEK JUNG

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

公开(公告)号：US11792982B2

公开(公告)日：2023-10-17

申请号：US17026377

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Hojun Seong ,  Joonhee Lee ,  Joon-Sung Lim ,  Euntaek Jung

IPC: H01L27/11582 ,  H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

公开(公告)号：US11024640B2

公开(公告)日：2021-06-01

申请号：US16514557

申请日：2019-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Jiyoung Kim ,  Jiwon Kim ,  Woosung Yang

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11551 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11565

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern.

公开(公告)号：US10804363B2

公开(公告)日：2020-10-13

申请号：US16445815

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Jiyoung Kim ,  Jiwon Kim ,  Woosung Yang

IPC: H01L29/417 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device comprises a substrate that includes a cell array region and a connection region, an electrode structure that includes a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate and has a stepwise structure on the connection region, an etch stop pattern that covers the stepwise structure of the electrode structure. The electrode structure and the etch stop pattern extend in a first direction when viewed in plan. The electrode structure has a first width in a second direction intersecting the first direction. The etch stop pattern has a second width in the second direction. The second width is less than the first direction.