公开(公告)号：US20190074380A1

公开(公告)日：2019-03-07

申请号：US16120705

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin PARK ,  Jin-bum Kim ,  Bong-soo Kim ,  Kyu-pil Lee ,  Hyeong-sun Hong ,  Yoo-sang Hwang

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/86 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

公开(公告)号：US20190074180A1

公开(公告)日：2019-03-07

申请号：US16120775

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin PARK ,  Bong-soo Kim ,  Jin-bum Kim ,  Yoo-sang Hwang

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming a transition metal oxide pattern on a substrate and forming a transition metal dichalcogenide layer on a top surface and a side surface of a residual portion of the transition metal oxide pattern. The forming the transition metal dichalcogenide layer may include replacing a surface portion of the transition metal oxide pattern with the transition metal dichalcogenide layer. The transition metal dichalcogenide layer includes at least one atomic layer that is substantially parallel to a surface of the residual portion of the transition metal oxide pattern.

公开(公告)号：US20160322362A1

公开(公告)日：2016-11-03

申请号：US15207554

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Yoo-sang Hwang ,  Ji-young Kim

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L27/10823 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.

Abstract translation: 一种制造半导体器件的方法包括：通过在第一方向上设置的第一凹槽彼此间隔开的位线结构，在第一方向上延伸并且在垂直于第一方向的第二方向上彼此间隔开，在基底上， 线被埋葬 在位线结构的两个侧壁上形成多层隔板; 形成牺牲层以填充第一凹槽; 通过图案化牺牲层形成在第一方向和第二方向上彼此间隔开的第二凹槽; 蚀刻位于第二凹槽中的多层间隔物的最外层间隔; 在第二槽中形成第一辅助间隔件; 形成绝缘层以填充第二凹槽; 以及通过去除牺牲层和绝缘层，在第一辅助隔离物的两侧上，在第一方向和第二方向上形成彼此间隔开的第三槽。

公开(公告)号：US09437560B2

公开(公告)日：2016-09-06

申请号：US14606245

申请日：2015-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-min Park ,  Yoo-sang Hwang

IPC: H01L23/52 ,  H01L23/00 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L24/02 ,  H01L24/08 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/15313

Abstract: A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact hole. The insulating spacer structure is adjacent a side wall of at least one of the conductive lines. The device also includes an insulating pattern on the conductive lines and insulating spacer structure, and another insulating pattern defining a landing pad hole connected to the contact hole. A contact plug is formed in the contact hole and connects to the active area. A landing pad is formed in the landing pad hole and connects to the contact plug. The landing pad vertically overlaps one of the pair of conductive line structures.

Abstract translation: 半导体器件包括与衬底间隔开的导线，以及在导线之间的绝缘间隔结构，并限定接触孔。 绝缘间隔物结构邻近至少一条导电线的侧壁。 该装置还包括导电线上的绝缘图案和绝缘间隔结构，以及限定连接到接触孔的着陆焊盘孔的另一绝缘图案。 接触插塞形成在接触孔中并且连接到有源区域。 着陆垫形成在着陆垫孔中并连接到接触塞。 着陆垫垂直地重叠一对导线结构之一。