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21.发明公开公开(公告)号：US20240170085A1
公开(公告)日：2024-05-23
申请号：US18200709
申请日：2023-05-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hojun YOON , Youngdon CHOI , Seungjin PARK , Seunghoon LEE , Junghwan CHOI
CPC classification number: G11C29/12015 , G11C7/222 , G11C8/18 , H03K5/1565
Abstract: A semiconductor device has a memory controller configured to provide a data strobe signal, and a memory device configured to receive a data signal provided from the memory controller or output a data signal to the memory controller, wherein the memory device includes a memory interface including a plurality of DQ driving circuits, the memory interface being configured to generate a plurality of phase clock signals based on the data strobe signal, determine a number of phase clock signals provided to the plurality of DQ driving circuits based on an operating frequency of the memory device, and provide the determined number of phase clock signals to the plurality of DQ driving circuits.
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22.发明公开公开(公告)号：US20230410917A1
公开(公告)日：2023-12-21
申请号：US18100173
申请日：2023-01-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hojun YOON , Jinha HWANG , Seunghoon LEE , Youngchul CHO , Youngdon CHOI , Junghwan CHOI
Abstract: An input/output circuit of a nonvolatile memory device and a nonvolatile memory device. The input/output circuit of a nonvolatile memory device includes a driver, which is configured to output data from the nonvolatile memory device to a data line, and a power gating circuit, which is connected between the driver and a power terminal or between the driver and a ground terminal and configured to block a leakage current of the driver. The power gating circuit includes a plurality of transistors electrically connected in parallel and having threshold voltages of different magnitudes, respectively.
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公开(公告)号：US20230395133A1
公开(公告)日：2023-12-07
申请号：US18449066
申请日：2023-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyoung PARK , Younghoon SON , Hyunyoon CHO , Youngdon CHOI , Junghwan CHOI
IPC: G11C11/4093 , G06F13/16 , G11C11/4076
CPC classification number: G11C11/4093 , G06F13/1668 , G11C11/4076
Abstract: In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
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Patent Agency Ranking
公开(公告)号：US20220414032A1
公开(公告)日：2022-12-29
申请号：US17903240
申请日：2022-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungmin JIN , Jindo BYUN , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
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公开(公告)号：US20220123967A1
公开(公告)日：2022-04-21
申请号：US17563406
申请日：2021-12-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaewoo PARK , Youngdon CHOI , Junghwan CHOI , Changsik YOO
Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.
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公开(公告)号：US20220059155A1
公开(公告)日：2022-02-24
申请号：US17230519
申请日：2021-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeokjun CHOI , Jindo BYUN , Yonghoon SON , Youngdon CHOI , Junghwan CHOI
IPC: G11C11/4091 , G11C11/4076 , G11C11/408 , G11C11/4096 , G11C11/406
Abstract: A semiconductor device includes: a multi-level receiver including N sense amplifiers and a decoder decoding an output of the N sense amplifiers, each of the N sense amplifiers receiving a multi-level signal having M levels and a reference signal (where M is a natural number, higher than 2, and where N is a natural number, lower than M); a clock buffer receiving a reference clock signal; and a clock controller generating N clock signals using the reference clock signal, inputting the N clock signals to the N sense amplifiers, respectively, and individually determining a phase of each of the N clock signals using the output of the N sense amplifiers.
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公开(公告)号：US20220059139A1
公开(公告)日：2022-02-24
申请号：US17323009
申请日：2021-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyoung PARK , Jaewoo PARK , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.
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公开(公告)号：US20210377080A1
公开(公告)日：2021-12-02
申请号：US17156813
申请日：2021-01-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaewoo PARK , Youngdon CHOI , Junghwan CHOI , Changsik YOO
Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.
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