公开(公告)号：US07529071B2

公开(公告)日：2009-05-05

申请号：US11535719

申请日：2006-09-27

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： H02H3/22

CPC分类号： H03K17/063

摘要： A circuit for selectively bypassing a capacitive element includes at least one NMOS device selectively connectable across the capacitive element to be bypassed, and at least first and second PMOS devices. The PMOS devices are selectively connectable together in series across the capacitive element to be bypassed. The NMOS device provides a first bypass path and the first and second PMOS devices collectively provide a second bypass path.

摘要翻译： 用于选择性地绕过电容元件的电路包括至少一个可选择地连接在待旁路的电容元件上的NMOS器件，以及至少第一和第二PMOS器件。 PMOS器件可选择性地连接在电容元件上串联在一起以被旁路。 NMOS器件提供第一旁路路径，并且第一和第二PMOS器件共同提供第二旁路路径。

公开(公告)号：US07498860B2

公开(公告)日：2009-03-03

申请号：US11691590

申请日：2007-03-27

申请人： Dipankar Bhattacharya ,  Carol A. Huber ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Carol A. Huber ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03L5/00

CPC分类号： H03K19/017581 ,  H03K19/01759

摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.

摘要翻译： 作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。 缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。 输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。 缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。

公开(公告)号：US20090002017A1

公开(公告)日：2009-01-01

申请号：US11768496

申请日：2007-06-26

申请人： Dipankar Bhattacharya ,  Gregg R. Harleman ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Gregg R. Harleman ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03K19/0175 ,  H03K19/02

CPC分类号： H03K19/00376

摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.

摘要翻译： 以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。 输出块的各输出端连接在一起形成缓冲电路的输出。 输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。 每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。 提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等价于第一模式中的二进制码字的算术移位。

公开(公告)号：US20080297226A1

公开(公告)日：2008-12-04

申请号：US11755955

申请日：2007-05-31

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

IPC分类号： G06G7/12

CPC分类号： H03K19/00384 ,  H04L5/16 ,  H04L25/0264

摘要： A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.

摘要翻译： 用于补偿至少第一MOS器件的输出阻抗的补偿电路，其中PVT变化对其可能经受的PVT变化包括：第一电流源，其产生具有基本恒定值的第一电流和产生第一MOS器件的第二电流源 第二电流具有可被编程为呈现给第二电流源的至少一个控制信号的函数的值。 比较器连接到第一和第二电流源的相应输出，并且可操作以测量第一和第二电流的相应值之间的差，并产生指示第一电流和第二电流的相对幅度的输出信号。 连接在比较器和第二电流源之间的反馈装置中的处理器接收比较器产生的输出信号，并产生用于根据输出信号控制第二电流的控制信号。 处理器可操作以控制第二电流的值，使得第二电流基本上等于第一电流。

公开(公告)号：US07391825B2

公开(公告)日：2008-06-24

申请号：US11046995

申请日：2005-01-31

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H04B10/06

CPC分类号： H03K5/2481 ,  H03K5/12

摘要： A comparator circuit having reduced pulse width distortion includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. An output stage is included in the comparator circuit for receiving the difference signal and for generating an output signal of the comparator circuit, the output signal being representative of the difference signal, the output stage having a switching point associated therewith. The comparator circuit further includes a voltage source coupled to the output of the differential amplifier. The voltage source is operative to generate a reference signal for establishing a common-mode voltage of the difference signal generated by the differential amplifier. The reference signal is substantially centered about the switching point of the output stage and substantially tracks the switching point over variations in process, voltage and/or temperature conditions to which the comparator circuit is subjected.

摘要翻译： 具有减小的脉冲宽度失真的比较器电路包括差分放大器，其操作以接收至少第一和第二信号并且放大第一和第二信号之间的差。 差分放大器在其输出处产生差分信号，其作为第一和第二信号之间的差异的函数。 输出级包括在比较器电路中，用于接收差分信号并产生比较器电路的输出信号，该输出信号代表差分信号，输出级具有与之相关的切换点。 比较器电路还包括耦合到差分放大器的输出的电压源。 电压源用于产生用于建立由差分放大器产生的差分信号的共模电压的参考信号。 参考信号基本上以输出级的切换点为中心，并且基本上跟踪比较器电路所经受的过程，电压和/或温度条件变化的切换点。

公开(公告)号：US07098694B2

公开(公告)日：2006-08-29

申请号：US10988103

申请日：2004-11-12

申请人： Dipankar Bhattacharya ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03K19/175

CPC分类号： H03K19/00315

摘要： When a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transistor in such a way that it is turned OFF when an overvoltage is applied, but turned ON when a normal voltage is applied. Another embodiment has two N-channel devices (M12, M13) coupled in series with each other and one of the N-channel devices (M13) being configured in a “turned off” position, by coupling the source and gate terminals to a ground voltage (VSS) and providing the supply voltage (VDD) at the gate terminal of another N-channel device (M12), whereby the device M12 protects the device M13 from overvoltage.

摘要翻译： 当P沟道栅极晶体管与N沟道栅极并联并联时，得到的电路提高了输入缓冲器的过压容差。 包括两个小晶体管的简单偏置电路以这样的方式控制该P沟道栅极晶体管的栅极，使得当施加过电压时其被截止，而当施加正常电压时，该栅极导通。 另一个实施例具有彼此串联耦合的两个N沟道器件（M12，M13），并且N沟道器件（M13）中的一个被配置为处于“截止”位置，通过将源极和栅极端子 接地电压（VSS），并在另一N沟道器件（M12）的栅极端提供电源电压（VDD），由此器件M 12保护器件M 13免受过压。

公开(公告)号：US07057545B1

公开(公告)日：2006-06-06

申请号：US11170127

申请日：2005-06-29

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03M1/12

CPC分类号： H01L28/20 ,  H01L27/0802

摘要： A semiconductor resistor circuit having a controllable resistance associated therewith includes a plurality of resistor segments connected in a series and/or parallel configuration. The resistor circuit further includes a plurality of switches controlling connection of respective ones of the resistor segments to the resistor circuit, to thereby selectively control a resistance of the resistor circuit in response to respective control signals presented to the switches. The resistor circuit is selectively controllable in discrete resistance intervals, the resistance intervals being unequal to one another. The resistor segments have resistance values that are selected such that a percentage resistance variation across each of the respective resistance intervals as a function of process, voltage and/or temperature conditions to which the resistor circuit is subjected is substantially the same.

摘要翻译： 具有与其相关联的可控电阻的半导体电阻器电路包括以串联和/或并联配置连接的多个电阻器段。 电阻电路还包括多个开关，其控制各个电阻器段与电阻器电路的连接，从而响应于提供给开关的相应控制信号选择性地控制电阻器电路的电阻。 电阻电路可以以离散的电阻间隔选择性地控制，电阻间隔彼此不相等。 电阻器段具有电阻值，其被选择为使得作为电阻器电路经受的过程，电压和/或温度条件的函数的各个电阻间隔中的每个电阻变化的百分比电阻变化基本相同。

公开(公告)号：US07869300B2

公开(公告)日：2011-01-11

申请号：US12431876

申请日：2009-04-29

申请人： Dharmeshkumar N. Bhakta ,  John C. Kriz ,  Eric D. Persson

发明人： Dharmeshkumar N. Bhakta ,  John C. Kriz ,  Eric D. Persson

IPC分类号： G11C5/14

CPC分类号： G11C8/18 ,  G06F1/3225 ,  G11C5/04 ,  G11C5/063 ,  G11C5/144 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C2211/4067

摘要： In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.

摘要翻译： 在存储器电路中，为了确保诸如DDR3 RDIMM之类的存储器件在存储器控制器断电和关断的情况下安全地在自刷新模式下操作，存储器件的时钟使能（CKE）输入连接到（i） 由存储器控制器施加的CKE信号和（ii）由功率模块提供的终端电压。 为了关闭存储控制器电源，存储控制器将CKE信号驱动为低电平，电源模块将端接电压驱动为低电平，电源模块关闭存储控制器。 要恢复正常操作，电源模块上电存储控制器，然后存储器控制器将CKE信号驱动为低电平，则电源模块将上电终止电压。 通过将端接电压保持在低电平，存储器电路确保存储器件在存储器件断电和关断时保持自刷新模式。

公开(公告)号：US20100278000A1

公开(公告)日：2010-11-04

申请号：US12431876

申请日：2009-04-29

申请人： Dharmeshkumar N. Bhakta ,  John C. Kriz ,  Eric D. Persson

发明人： Dharmeshkumar N. Bhakta ,  John C. Kriz ,  Eric D. Persson

IPC分类号： G11C5/14 ,  G06F1/04 ,  G06F1/26 ,  G06F12/00

CPC分类号： G11C8/18 ,  G06F1/3225 ,  G11C5/04 ,  G11C5/063 ,  G11C5/144 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C2211/4067

摘要： In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.

摘要翻译： 在存储器电路中，为了确保诸如DDR3 RDIMM之类的存储器件在存储器控制器断电和关断的情况下安全地在自刷新模式下操作，存储器件的时钟使能（CKE）输入连接到（i） 由存储器控制器施加的CKE信号和（ii）由功率模块提供的终端电压。 为了关闭存储控制器电源，存储控制器将CKE信号驱动为低电平，电源模块将端接电压驱动为低电平，电源模块关闭存储控制器。 要恢复正常操作，电源模块上电存储控制器，然后存储器控制器将CKE信号驱动为低电平，则电源模块将上电终止电压。 通过将端接电压保持在低电平，存储器电路确保存储器件在存储器件断电和关断时保持自刷新模式。

公开(公告)号：US07196561B2

公开(公告)日：2007-03-27

申请号：US10925613

申请日：2004-08-25

申请人： Dipankar Bhattacharya ,  John C. Kriz ,  Duane J. Loeper ,  Antonio M. Marques

发明人： Dipankar Bhattacharya ,  John C. Kriz ,  Duane J. Loeper ,  Antonio M. Marques

IPC分类号： H03L7/00

CPC分类号： H03K17/223

摘要： A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage. The second voltage is less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.

摘要翻译： 用于产生复位信号的PUR电路包括用于接收参考电压的第一节点和用于接收相对于参考电压参考的电源电压的第二节点。 电路还包括耦合在第一节点和第三节点之间的电压电平检测器，电压电平检测器被配置为在第三节点处产生第一控制信号。 电压电平检测器包括具有与其相关联的第一阈值电压的第一晶体管。 电阻元件耦合在第二节点和第三节点之间，电阻元件具有与之相关联的第一电阻值。 该电路还包括具有耦合到第三节点并具有响应于第一控制信号产生第二控制信号的输出的反相器。 逆变器包括具有与其相关联的第二阈值电压的第二晶体管，其低于第一阈值电压。 电压电平检测器被配置为使得当电源电压小于第一电压时，第一控制信号基本上等于电源电压，并且当电源电压基本上等于或等于第一控制信号时，第一控制信号等于第二电压 大于第一电压。 第二电压小于逆变器的较低开关点，第一电压至少部分地基于第一阈值电压，复位信号是第二控制信号的函数。