-
21.
公开(公告)号:US5977642A
公开(公告)日:1999-11-02
申请号:US918085
申请日:1997-08-25
IPC分类号: H01L21/48 , H01L21/56 , H01L21/60 , H01L23/498 , H05K3/32 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号: H01L24/81 , H01L21/4853 , H01L21/563 , H01L23/49811 , H05K3/325 , H01L2224/13144 , H01L2224/16225 , H01L2224/73203 , H01L2224/81801 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H05K2201/10734 , H05K2201/10977 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
摘要: A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.
摘要翻译: 提供了一种用于连接电子电路封装中的两个导电表面的方法,包括以下步骤:在第一导电表面的选定区域上形成枝晶,在第一导电表面上施加介电绝缘材料,使得枝晶通过绝缘材料暴露于 留下暴露的树突的基本上平坦的表面,并将第二导电表面放置在暴露的树突上。 第二导电表面可以是表面金属,芯片凸块阵列或球栅阵列。 还要求保护的是包含用于根据本发明制造的电互连和平坦化的树突的电子电路封装。