-
1.发明授权Conductor interconnect with dendrites through film and method for producing same 失效导体通过薄膜与树突互连，以及用于制造它的方法公开(公告)号：US06256874B1
公开(公告)日：2001-07-10
申请号：US09315305
申请日：1999-05-20
IPC分类号： H05K336
CPC分类号： H05K3/325 , H05K3/4614 , H05K2201/0373 , H05K2201/09536 , H05K2201/10666 , Y10T29/49126 , Y10T29/49128 , Y10T29/49165 , Y10T29/49194
摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”
摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料 并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。 还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。 本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。
-
公开(公告)号：US06739046B1
公开(公告)日：2004-05-25
申请号：US09576641
申请日：2000-05-22
IPC分类号： H05K302
CPC分类号： H01L24/81 , H01L21/4853 , H01L21/563 , H01L23/49811 , H01L2224/13144 , H01L2224/16225 , H01L2224/73203 , H01L2224/81801 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H05K3/325 , H05K2201/10734 , H05K2201/10977 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , H01L2924/00
摘要： A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.
摘要翻译： 提供了一种用于连接电子电路封装中的两个导电表面的方法，包括以下步骤：在第一导电表面的选定区域上形成枝晶，在第一导电表面上施加介电绝缘材料，使得枝晶通过绝缘材料暴露于 留下暴露的树突的基本上平坦的表面，并将第二导电表面放置在暴露的树突上。 第二导电表面可以是表面金属，芯片凸块阵列或球栅阵列。 还要求保护的是包含用于根据本发明制造的电互连和平坦化的树突的电子电路封装。
-
公开(公告)号：US06300575B1
公开(公告)日：2001-10-09
申请号：US08918084
申请日：1997-08-25
IPC分类号： H05K114
CPC分类号： H05K3/325 , H05K3/4614 , H05K2201/0373 , H05K2201/09536 , H05K2201/10666 , Y10T29/49126 , Y10T29/49128 , Y10T29/49165 , Y10T29/49194
摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”
摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料 并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。 还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。 本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。
-
公开(公告)号：US06427323B2
公开(公告)日：2002-08-06
申请号：US09859690
申请日：2001-05-17
IPC分类号： H05K336
CPC分类号： H05K3/325 , H05K3/4614 , H05K2201/0373 , H05K2201/09536 , H05K2201/10666 , Y10T29/49126 , Y10T29/49128 , Y10T29/49165 , Y10T29/49194
摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”
摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料 并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。 还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。 本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。
-
公开(公告)号：US5977642A
公开(公告)日：1999-11-02
申请号：US918085
申请日：1997-08-25
IPC分类号： H01L21/48 , H01L21/56 , H01L21/60 , H01L23/498 , H05K3/32 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/81 , H01L21/4853 , H01L21/563 , H01L23/49811 , H05K3/325 , H01L2224/13144 , H01L2224/16225 , H01L2224/73203 , H01L2224/81801 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H05K2201/10734 , H05K2201/10977 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
摘要： A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.
摘要翻译： 提供了一种用于连接电子电路封装中的两个导电表面的方法，包括以下步骤：在第一导电表面的选定区域上形成枝晶，在第一导电表面上施加介电绝缘材料，使得枝晶通过绝缘材料暴露于 留下暴露的树突的基本上平坦的表面，并将第二导电表面放置在暴露的树突上。 第二导电表面可以是表面金属，芯片凸块阵列或球栅阵列。 还要求保护的是包含用于根据本发明制造的电互连和平坦化的树突的电子电路封装。
-
6.发明授权Thermally enhanced and mechanically balanced flip chip package and method of forming 失效热增强和机械平衡倒装芯片封装和成型方法公开(公告)号：US06410988B1
公开(公告)日：2002-06-25
申请号：US09570895
申请日：2000-05-15
申请人： David V. Caletka , Jean Dery , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson , Luis J. Matienzo , James R. Wilcox
发明人： David V. Caletka , Jean Dery , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson , Luis J. Matienzo , James R. Wilcox
IPC分类号： H01L2348
CPC分类号： H01L23/4334 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/10253 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2924/3512
摘要： A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.
摘要翻译： 描述了制造在宽温度范围内保持平坦度并提供良好散热的倒装芯片封装的方法。 层压基板电连接到设置在芯片上的电触头，底部填充材料被施加在焊接连接之间。 例如未固化介电材料的主体被施加到芯片，层压基板，导热构件或其组合，并且导热构件设置在与连接到层压板的表面相对的芯片的表面附近 基质。 主体在芯片和导热构件之间挤出。 导热构件的厚度通过平衡导热构件和层压衬底的刚度和CTE来确定，并且导热构件的长度和宽度可以变化，但是至少为相应长度的尺寸，并且 芯片的宽度。
-
公开(公告)号：US6104093A
公开(公告)日：2000-08-15
申请号：US80117
申请日：1998-05-15
申请人： David V. Caletka , Jean Dery , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson , Luis J. Matienzo , James R. Wilcox
发明人： David V. Caletka , Jean Dery , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson , Luis J. Matienzo , James R. Wilcox
IPC分类号： H01L23/31 , H01L23/433 , H01L23/48
CPC分类号： H01L23/4334 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/10253 , H01L2924/15311
摘要： A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.
-
公开(公告)号：US07255571B2
公开(公告)日：2007-08-14
申请号：US11521158
申请日：2006-09-14
申请人： William L. Brodsky , James A. Busby , Bruce J. Chamberlin , Mitchell G. Ferrill , Robin A. Susko , James R. Wilcox
发明人： William L. Brodsky , James A. Busby , Bruce J. Chamberlin , Mitchell G. Ferrill , Robin A. Susko , James R. Wilcox
IPC分类号： H01R12/00
CPC分类号： H01L23/49811 , H01L24/16 , H01L24/81 , H01L2224/0501 , H01L2224/05011 , H01L2224/05026 , H01L2224/05548 , H01L2224/056 , H01L2224/81141 , H01L2224/81191 , H01L2224/81193 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , H01L2924/12044 , H01L2924/14 , H01L2924/30107 , H01R4/01 , H01R12/52 , H05K3/325 , H05K2201/068 , H05K2201/209 , H05K2203/1105 , H01L2224/05099
摘要： A method and structure is disclosed for forming a removable interconnect for semiconductor packages, where the connector is adapted to repeatedly change from a first shape into a second shape upon being subjected to a temperature change and to repeatedly return to the first shape when not being subjected to the temperature change. The connector can be disconnected when the connector is in its second shape and the connector cannot be disconnected when the connector is in its first shape.
摘要翻译： 公开了一种用于形成用于半导体封装的可移除互连的方法和结构，其中连接器适于在经受温度变化时从第一形状重复地变为第二形状，并且在不受影响时重复地返回到第一形状 到温度变化。 当连接器处于其第二形状时，连接器可以断开，并且当连接器处于其第一形状时连接器不能断开。
-
公开(公告)号：US07128579B1
公开(公告)日：2006-10-31
申请号：US11161858
申请日：2005-08-19
申请人： William L. Brodsky , James A. Busby , Bruce J. Chamberlin , Mitchell G. Ferrill , Robin A. Susko , James R. Wilcox
发明人： William L. Brodsky , James A. Busby , Bruce J. Chamberlin , Mitchell G. Ferrill , Robin A. Susko , James R. Wilcox
IPC分类号： H01R12/00
CPC分类号： H01R12/523 , H01R12/58 , Y10S439/907 , Y10S439/908
摘要： Disclosed is a semiconductor package structure that incorporates the use of conductive pins to electrically and mechanically connect a semiconductor module and a substrate (e.g., printed wiring board). Specifically, one or both ends of the pins are hooked and are adapted to allow a press-fit connection with the walls of the plated through holes of either one or both of the semiconductor module and the substrate. The hook-shaped ends of the pins may have one or more hooks to establish the connection. Additionally, the pins may be formed of a temperature induced shape change material that bends to allow engaging and/or disengaging of the hook-shaped ends from the walls of the plated through holes.
摘要翻译： 公开了一种半导体封装结构，其结合使用导电引脚来电和机械地连接半导体模块和基板（例如，印刷线路板）。 具体地，销的一端或两端被钩住并且适于允许与半导体模块和衬底中的一个或两者的电镀通孔的壁压合连接。 销的钩形端可以具有一个或多个钩以建立连接。 此外，销可以由温度诱导的形状变化材料形成，该材料弯曲以允许钩状端部与电镀通孔的壁接合和/或脱离。
-
公开(公告)号：US07024764B2
公开(公告)日：2006-04-11
申请号：US10040745
申请日：2002-01-07
IPC分类号： H05K3/34
CPC分类号： H01L23/49822 , H01L23/3735 , H01L2224/16225 , H01L2924/00014 , H01L2924/01322 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4641 , H05K2201/0191 , H05K2201/068 , H05K2201/09536 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , H01L2924/00 , H01L2224/0401
摘要： A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.
摘要翻译： 制作电子包装的方法。 该方法包括形成半导体芯片和多层互连结构。 半导体芯片包括通过多个焊接连接而连接到多层互连结构的其一个表面上的多个接触构件。 形成的多层互连结构适于将半导体芯片与另外多个焊接连接的电路化基板（例如，电路板）电互连，并且包括导热层，其由具有选定厚度和系数的材料组成 热膨胀以基本上防止所述第一多个导电构件和半导体芯片之间的焊料连接的故障。 该方法形成电子封装以进一步包括具有有效模数的电介质材料，以确保在操作期间多层互连结构的充分符合性。
-
-
-
-
-
-
-
-
-
搜索结果
22 条记录 (耗时 0.027 秒)
