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37 条记录 (耗时 0.029 秒)

    Packet switch device
    21.
    发明授权
    Packet switch device 失效
    分组交换设备

    公开(公告)号：US07227861B2

    公开(公告)日：2007-06-05

    申请号：US09805545

    申请日：2001-03-13

    申请人： Hiroshi Tomonaga ,  Masakatsu Nagata ,  Kenichi Kawarai ,  Naoki Matsuoka ,  Kenichi Okabe ,  Shiro Uriu

    发明人： Hiroshi Tomonaga ,  Masakatsu Nagata ,  Kenichi Kawarai ,  Naoki Matsuoka ,  Kenichi Okabe ,  Shiro Uriu

    IPC分类号： H04L12/56

    CPC分类号： H04Q11/0421 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13296

    摘要： Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.

    摘要翻译： 从输入HW＃0到＃3输入到分组交换设备的分组被掩埋在时隙A到D中。分组交换设备以时隙为单位交替地切换输入分组，并将分组输入到两个4×4交换机。 4x4交换机进行正常交换，并将数据包分配到相应的输出端口。 然后，在切换之后从两个4×4交换机输出的分组交替复用，并输出到输出HW＃0至＃3。 通过如上所述进行分组的切换，防止了处理开销的增加，并且也可以容易地进行扩展。 此外，硬件规模可以减小。

    Address creator and arithmetic circuit
    22.
    发明申请
    Address creator and arithmetic circuit 审中-公开
    地址创建者和算术电路

    公开(公告)号：US20060004980A1

    公开(公告)日：2006-01-05

    申请号：US11034862

    申请日：2005-01-14

    申请人： Mitsuharu Wakayoshi ,  Shiro Uriu

    发明人： Mitsuharu Wakayoshi ,  Shiro Uriu

    IPC分类号： G06F12/00

    CPC分类号： G06F9/3885 ,  G06F9/345 ,  G06F9/3891

    摘要： A plurality of address creators are provided corresponding to a plurality of memories of ALU modules. The address creators create addresses for reading or writing data from the memories each time a connection configuration is switched. In creating addresses in the memories, the address creators enable operations to be set by using various types of parameters and set values by mounting special-purpose hardware for memory ports, so that addresses can be created at high-speed.

    摘要翻译： 对应于ALU模块的多个存储器提供多个地址创建者。 每次连接配置切换时，地址创建者创建地址来读取或写入数据。 在创建存储器中的地址时，地址创建者可以通过使用各种类型的参数来设置操作，并通过为存储器端口安装专用硬件设置值，从而可以高速创建地址。

    Apparatus for preventing malfunction at time of duplex unit failure
    24.
    发明授权
    Apparatus for preventing malfunction at time of duplex unit failure 失效
    双机故障时防止故障的装置

    公开(公告)号：US5958069A

    公开(公告)日：1999-09-28

    申请号：US854741

    申请日：1997-05-12

    申请人： Hiroya Kawasaki ,  Masaki Kira ,  Shiro Uriu ,  Yukinaga Toyoda ,  Kazumasa Sonoda

    发明人： Hiroya Kawasaki ,  Masaki Kira ,  Shiro Uriu ,  Yukinaga Toyoda ,  Kazumasa Sonoda

    IPC分类号： H04M3/22 ,  G06F11/20 ,  H04L29/14 ,  G06F11/16

    CPC分类号： G06F11/2025 ,  G06F11/2038 ,  G06F11/2041

    摘要： A system includes a host, first and second devices which operate as an acting device and a standby device, and a simplex unit controlled by the acting device. Each device is provided with a monitoring unit for monitoring the occurrence of failure, means for notifying the other device of a failure in its own device, and active/standby notification means. The active/standby notification means notifies the simplex unit that its own device is acting or standing by when the device becomes the acting device or standby device in response to a command from the host. Upon a failure in the other device when its own device is standing by, the active/standby notification means notifies the simplex unit that its own device is now an apparent acting device. Upon a failure in its own device when its own device is acting, the active/standby notification means notifies the simplex unit that its own device is now an apparent standby device. The simplex unit executes predetermined control upon accepting control data from the apparent acting device.

    摘要翻译： 系统包括作为作用装置和备用装置操作的主机，第一和第二装置以及由作用装置控制的单工装置。 每个设备设置有用于监视故障发生的监视单元，用于通知其他设备在其自己的设备中的故障的装置以及主动/备用通知装置。 主动/待机通知装置响应于来自主机的命令，当设备成为作用设备或备用设备时，通知单机设备本身正在行动或站立的设备。 当其他设备在其自身设备待机时发生故障时，主动/待机通知单元通知单机单元其自己的设备现在是表观动作设备。 当自己的设备在其自身的设备发生故障时，主动/备用通知装置通知单工装置其自己的设备现在是明显的待机设备。 单体单元在接受来自视在动作装置的控制数据时执行预定的控制。

    Reconfigurable operation apparatus
    26.
    发明申请
    Reconfigurable operation apparatus 有权
    可重构操作装置

    公开(公告)号：US20060010306A1

    公开(公告)日：2006-01-12

    申请号：US11077561

    申请日：2005-03-11

    申请人： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

    发明人： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

    IPC分类号： G06F15/00

    CPC分类号： G06F15/8007

    摘要： A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

    摘要翻译： 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

    Array processor having reconfigurable data transfer capabilities
    28.
    发明授权
    Array processor having reconfigurable data transfer capabilities 有权
    阵列处理器具有可重新配置的数据传输能力

    公开(公告)号：US07774580B2

    公开(公告)日：2010-08-10

    申请号：US11077561

    申请日：2005-03-11

    申请人： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

    发明人： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

    IPC分类号： G06F15/00 ,  G06F15/76

    CPC分类号： G06F15/8007

    摘要： A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

    摘要翻译： 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

    Address release method, and common buffering device for ATM switching system which employs the same method
    29.
    发明授权
    Address release method, and common buffering device for ATM switching system which employs the same method 失效
    地址释放方法和采用相同方法的ATM交换系统的通用缓冲装置

    公开(公告)号：US06789176B2

    公开(公告)日：2004-09-07

    申请号：US09286332

    申请日：1999-04-05

    申请人： Shiro Uriu ,  Masanobu Furukoshi ,  Tetsuaki Wakabayashi ,  Kazumasa Sonoda

    发明人： Shiro Uriu ,  Masanobu Furukoshi ,  Tetsuaki Wakabayashi ,  Kazumasa Sonoda

    IPC分类号： G06F1206

    CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L2012/5681

    摘要： In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.

    摘要翻译： 在具有简单布置的公共缓冲装置中，在接收到多地址呼叫时，可以从缓冲存储器高效地释放写入地址。 对于要发送到特定线路的ATM信元，在公共缓冲存储器中设置写入地址，并且将ATM信元写入写入地址。 ATM单元从对应于写入地址的地址读取，并被发送到特定的行。 然后，释放相关的写入地址。 在写入表中输入多个多地址线，在公共缓冲设备中以特定地址写入的ATM信元可以跨多路地址线进行组播。 每当从特定地址读取ATM信元时，将读取控制表中的ATM信元的发送指定行与设置在写入控制表中的多地址线进行比较。 当行匹配时，释放写入控制表中设置的ATM信元的写入地址。