公开(公告)号：US11923026B2

公开(公告)日：2024-03-05

申请号：US17394738

申请日：2021-08-05

Applicant: Seagate Technology LLC

Inventor： Jeremy B. Goolsby ,  Ryan J. Goss ,  Indrajit Prakash Zagade ,  Thomas V. Spencer ,  Jeffrey J. Pream ,  Christopher A. Smith ,  Charles McJilton

IPC: G11C29/00 ,  G06F11/07 ,  G06F11/30 ,  G11C29/12 ,  G11C29/18 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G06F11/073 ,  G06F11/0766 ,  G06F11/3037 ,  G11C29/12005 ,  G11C29/18 ,  G11C29/4401

Abstract: A data storage system may connect a non-volatile memory to a quarantine module that generates a quarantine strategy in response to a pending data access request to the non-volatile memory. The quarantine strategy can proactively prescribing a plurality of status levels for physical data addresses of the non-volatile memory. A comparison of a volume of errors for the non-volatile memory to a first threshold of the quarantine strategy with the quarantine module may prompt the alteration of a first status level of the plurality of status levels for a first physical data address of the non-volatile memory, as directed by the quarantine strategy.

公开(公告)号：US11810625B2

公开(公告)日：2023-11-07

申请号：US17499418

申请日：2021-10-12

Applicant: Seagate Technology LLC

Inventor： Ryan J. Goss ,  Christopher A. Smith ,  Indrajit Zagade ,  Jonathan Henze

IPC: G11C16/26 ,  G11C29/38 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C29/38 ,  G11C16/0483

Abstract: A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.

公开(公告)号：US11640336B2

公开(公告)日：2023-05-02

申请号：US17380655

申请日：2021-07-20

Applicant: Seagate Technology LLC

Inventor： Ryan J. Goss ,  Jack V. Anderson ,  Jonathan M. Henze

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: Method and apparatus for intelligent caching, protection and transfers of data between a cache and a main memory in a data storage environment, such as but not limited to a solid-state drive (SSD). A main memory (MM) has non-volatile memory (NVM) cells configured for persistent storage of user data. A fast response cache (FRC) has NVM cells configured to provide storage of first data prior to transfer to the MM. A write cache (WC) has NVM cells configured to provide storage of second data prior to transfer to the MM. A controller directs input data to either the FRC or the WC. A first type of error correction encoding (ECC1) is applied to the first data and a different, second type of error correction encoding (ECC2) is applied to the second data. Data may be sent from the FRC to the MM either directly or through the WC.

公开(公告)号：US20180253235A1

公开(公告)日：2018-09-06

申请号：US15971871

申请日：2018-05-04

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Dana L. Simonson ,  Kristofer C. Conklin ,  Ryan J. Goss ,  Robert W. Moss ,  Stacey Secatch

IPC: G06F3/06

CPC classification number: G06F3/0605 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00

Abstract: Systems and methods for enhanced read recovery based on write time information are described. In one embodiment, the systems and methods include opening a block of flash memory cells for programming, tracking a block open time, and performing a read operation of a programmed page from the block based at least in part on the block open time. In some embodiments, the block includes a plurality of pages, each page including a plurality of flash memory cells. In some cases, the block open time includes an amount of time between the block opening for programming to a time the block closes for programming.

公开(公告)号：US20160188226A1

公开(公告)日：2016-06-30

申请号：US14936576

申请日：2015-11-09

Applicant: Seagate Technology LLC

Inventor： Jonathan W. Haines ,  Timothy R. Feldman ,  Wayne H. Vinson ,  Ryan J. Goss ,  Kevin Gomez ,  Mark Allen Gaertner

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.

Abstract translation: 一种示例性方法包括在存储器中提供至少两个数据存储区域，为所述至少两个数据存储区域中的第一个提供第一量的过度供应，以及为所述至少两个数据存储区域中的第二数据存储区域提供第二量的过度供应 数据存储区域，基于数据的特性对数据进行分类，并且基于分类将数据存储在至少两个数据存储区域之一中。