公开(公告)号：US07403044B2

公开(公告)日：2008-07-22

申请号：US11114130

申请日：2005-04-26

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03K5/22

CPC classification number: H03K5/04 ,  H03K5/135 ,  H03K5/26

Abstract: Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then transmits the UP or DOWN control signal to edge adjusting circuits connected to each strobe and data stream between the flip flop and pre-driver. The edge adjusting then adds a delay to each respective strobe and data stream which incrementally compensates for the mismatch created by PVT variations. The process is repeated until the high and low data outputs are effectively matched, thereby maximizing the data eye.

Abstract translation: 选通信号耦合到相位检测器，该相位检测器比较各个选通信号的上升沿和下降沿。 如果相位检测器确定存在不匹配，则向控制电路输出UP或DOWN控制信号。 然后，控制电路将UP或DOWN控制信号发送到连接到每个选通脉冲的边缘调整电路和触发器和预驱动器之间的数据流。 边缘调整然后对每个相应的选通和数据流添加一个延迟，增量地补偿由PVT变化产生的失配。 重复该过程，直到高和低数据输出被有效地匹配，从而使数据眼睛最大化。

公开(公告)号：US20080150598A1

公开(公告)日：2008-06-26

申请号：US12046652

申请日：2008-03-12

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/10

Abstract: A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effectively operate the loop at a lower frequency close to its own intrinsic bandwidth (1/tLoop) instead of at the higher frequency of the clock signal (1/tCK). To do so, in one embodiment, the loop delay, tLoop, is measured or estimated prior to operation of the loop. The phase detector is then enabled to operate close to the loop frequency, 1/tLoop. In short, the phase detector is made not to see activity during useless delay times, which prevents the loop from overreacting and becoming unstable.

Abstract translation: 公开了用于延迟锁定环（DLL）或锁相环（PLL）的方法和电路，其改善了高频下的环路稳定性，并允许最大跟踪带宽，而不管过程，电压或温度变化。 该技术的核心是以更接近其自身固有带宽（1 / tLoop）的较低频率有效地操作环路，而不是在时钟信号（1 / tCK）的较高频率处。 为了做到这一点，在一个实施例中，在循环操作之前测量或估计环路延迟t L oop。 然后，相位检测器使能接近环路频率1 / tLoop。 简而言之，使相位检测器在无用的延迟时间期间看不到活动，从而防止环路过度反应并变得不稳定。

公开(公告)号：US20080094116A1

公开(公告)日：2008-04-24

申请号：US11957333

申请日：2007-12-14

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03L7/06

CPC classification number: G11C7/1072 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/095 ,  H03L7/0995

Abstract: A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.

Abstract translation: 时钟发生电路包括相位比较电路，其产生对应于输出时钟信号和参考时钟信号的相对相位的延迟控制信号。 电压控制延迟电路通过反相施加到其输入的信号并延迟由延迟控制信号确定的延迟来产生延迟的时钟信号。 选择电路将参考时钟信号或延迟时钟信号耦合到电压控制延迟电路的输入端。 当参考时钟信号耦合到电压控制延迟电路的输入时，时钟发生电路用作延迟锁定环路。 当延迟时钟信号耦合到电压控制延迟电路的输入端时，电压控制延迟电路作为环形振荡器工作，使得时钟发生电路用作锁相环。

公开(公告)号：US5877653A

公开(公告)日：1999-03-02

申请号：US751703

申请日：1996-11-18

Applicant: Young Kim ,  Jong-Tae Park ,  Hong-Kee Kim ,  Young-Kon Lee ,  Seung-Won Chung ,  Seong-Hoon Lee ,  Soon-Chul Jeong ,  Chul-Dong Kim ,  Ik-Soo Chang

Inventor： Young Kim ,  Jong-Tae Park ,  Hong-Kee Kim ,  Young-Kon Lee ,  Seung-Won Chung ,  Seong-Hoon Lee ,  Soon-Chul Jeong ,  Chul-Dong Kim ,  Ik-Soo Chang

IPC: H03F1/26 ,  H03F1/32 ,  H03F3/20

CPC classification number: H03F1/3276 ,  H03F1/3229 ,  H03F1/3252 ,  H03F2201/3212

Abstract: A linear power amplifier and method for removing the intermodulation distortion with a predistortion system and a feed forward system. The linear power amplifier having a main power amplifier includes: a predistortion system for firstly suppressing the intermodulation signal generated upon amplification of an RF signal in the main power amplifier, by generating a harmonics corresponding to the input RF signal and a predistortion signal with coupling the RF signal to the harmonics; and a feed forward system for secondly suppressing the intermodulation signal by canceling the input RF signal and the output of the main power amplifier, extracting an intermodulation signal distortion, error-amplifying the extracted intermodulation signal distortion, and coupling the amplified intermodulation signal with the output of the main power amplifier.

Abstract translation: 一种线性功率放大器和用预失真系统和前馈系统去除互调失真的方法。 具有主功率放大器的线性功率放大器包括：预失真系统，用于首先抑制在主功率放大器中放大RF信号时产生的互调信号，通过产生与输入RF信号相对应的谐波和预失真信号， 射频信号到谐波; 以及前馈系统，用于通过消除输入RF信号和主功率放大器的输出来二次抑制互调信号，提取互调信号失真，误差放大所提取的互调信号失真，以及将放大的互调信号与输出 的主功率放大器。

公开(公告)号：US08947964B2

公开(公告)日：2015-02-03

申请号：US12820050

申请日：2010-06-21

Applicant: Onegyun Na ,  Jongtae Kwak ,  Seong-Hoon Lee ,  Hoon Choi

Inventor： Onegyun Na ,  Jongtae Kwak ,  Seong-Hoon Lee ,  Hoon Choi

IPC: G11C7/02 ,  G11C7/06 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C11/4074 ,  G11C2207/063 ,  G11C2207/2281

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract translation: 电流检测放大器可以包括耦合在放大器的差分输出节点之间的一个或多个钳位电路。 钳位电路可以在读出放大器感测耦合到读出放大器的差分输入的存储器单元的状态的至少一部分期间被使能。 在读出放大器以不同的时间以交错的方式感测存储器单元的状态的时间期间，钳位电路可能被禁用。 钳位电路可能正在使电流检测放大器对噪声信号较不敏感。

公开(公告)号：US08758077B2

公开(公告)日：2014-06-24

申请号：US12795100

申请日：2010-06-07

Applicant: Hong-Min Jang ,  Seong-Hoon Lee

Inventor： Hong-Min Jang ,  Seong-Hoon Lee

IPC: A63H13/06 ,  A63H29/22

CPC classification number: A63H13/06

Abstract: A fighter robot system that supplies power to two fighter robots, which have a match against each other, through respective power lines and prevents the power lines from becoming entangled even when the robots are moving. The fighter robot system includes two fighter robots, a power supply providing power to the fighter robots, and a rotary member located above or below the fighter robots, the rotary member having a predetermined length and rotatable around a central axis formed at a predetermined portion. The power supply provides the power to the fighter robots through power lines. Each power line starts from the power supply, extends from the central axis to either end of the rotary member in the lengthwise direction, and is connected at that end to each fighter robot. The rotary member rotates around the central axis following the movement of the fighter robots.

Abstract translation: 一种战斗机器人系统，通过各自的电源线向两个相互匹配的战斗机器人供电，即使在机器人移动时也能防止电力线缠结。 战斗机器人系统包括两个战斗机器人，为战斗机器人提供动力的电源，以及位于战斗机器人上方或下方的旋转构件，旋转构件具有预定长度并可围绕形成在预定部分的中心轴线旋转。 电源通过电源线为战斗机器人提供动力。 每个电源线从电源开始，从长轴方向的中心轴线延伸到旋转部件的任一端，并且在该端部连接到每个战斗机器人。 随着战斗机器人的移动，旋转构件围绕中心轴线旋转。

公开(公告)号：US08705304B2

公开(公告)日：2014-04-22

申请号：US12732968

申请日：2010-03-26

Applicant: Seong-Hoon Lee ,  Onegyun Na ,  Jongtae Kwak

Inventor： Seong-Hoon Lee ,  Onegyun Na ,  Jongtae Kwak

IPC: G11C7/00 ,  G11C7/02

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C2207/063

Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

Abstract translation: 公开了一种存储器，电流模式读出放大器及其操作方法，包括一个包括交叉耦合的p沟道晶体管和耦合到交叉耦合的p沟道晶体管的负载电路的电流模式读出放大器。 负载电路被配置为提供至少部分地控制电流模式读出放大器的环路增益的电阻，负载电路至少包括被动电阻。

公开(公告)号：US08581630B2

公开(公告)日：2013-11-12

申请号：US13235243

申请日：2011-09-16

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03K19/094 ,  H03K3/00 ,  H03B1/00 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C5/147 ,  H02M3/1563 ,  H03K17/687 ,  H03K19/018507 ,  H03K19/018585

Abstract: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

Abstract translation: 具有用于高逻辑电平输出信号的可调输出电压的信号驱动器电路。 信号驱动器电路包括：信号驱动器，被配置为输出具有第一电压的第一逻辑电平信号，并输出具有根据输入信号的第二电压的第二逻辑电平信号。 耦合到信号驱动器的电压控制电压电源为第一逻辑电平信号提供第一电压。 由压控电压提供的第一电压的大小基于偏置电压。 偏置电压发生器可以耦合到压控电压源以提供偏置电压。

公开(公告)号：US08289796B2

公开(公告)日：2012-10-16

申请号：US12694136

申请日：2010-01-26

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G11C7/02

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  H03F3/45179 ,  H03G3/00

Abstract: Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage.

Abstract translation: 公开了用于放大电流输入的存储器，感测放大器和放大电流输入的方法，包括读出放大器，其包括偏置电路，该偏置电路被配置为提供具有响应于保持基本上恒定的环路增益的幅度的偏置电压，并且还包括耦合到 偏置电路以接收所述偏置电压并且被配置为放大输入 - 输出节点处的输入电流，所述电流放大器级的环路增益至少部分地被控制为所述偏置电压。

公开(公告)号：US20110102020A1

公开(公告)日：2011-05-05

申请号：US12939869

申请日：2010-11-04

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G01R25/00

CPC classification number: H03D13/004

Abstract: Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.

Abstract translation: 公开了诸如涉及数字相位检测器的方法和装置，该数字相位检测器包括被配置为检测两个时钟信号中的哪一个引导另一个的相位检测电路。 一个这样的相位检测器包括配置成准备用于相位检测的相位检测电路的平衡器。 一个或多个实施例的相位检测电路包括交叉耦合锁存器，其配置为接收两个时钟信号，并响应于两个时钟信号产生第一锁存器输出和第二锁存器输出。 上述平衡器被配置为在相位检测电路检测到两个时钟信号之间的相位差之前基本均衡第一和第二锁存器输出的电压电平。 例如，平衡器可以在相位检测之前将相位检测电路的输出预充电至基本相同的电压电平。