公开(公告)号：US06473344B2

公开(公告)日：2002-10-29

申请号：US09952515

申请日：2001-09-13

申请人： Hyung-Gon Kim ,  Yeong-Taek Lee

发明人： Hyung-Gon Kim ,  Yeong-Taek Lee

IPC分类号： G11C1604

CPC分类号： G11C29/12 ,  G11C8/08

摘要： A semiconductor memory device includes a select signal generator, a wordline voltage generator, and a switch circuit. During a test operation mode, the device determine whether a wordline voltage has required level. The select signal generator activates one of select signals each corresponding to the other wordline voltages responsive to external select code signals. The external select code signals appoint an external instruction signal representative and appoint other wordline voltages used in the memory device. The wordline voltage generator generates a wordline voltage corresponding to the activated select signal out. The switch circuit transfers the wordline voltage outputted from the wordline voltage generator to a pad connected to an external pin.

摘要翻译： 半导体存储器件包括选择信号发生器，字线电压发生器和开关电路。 在测试操作模式期间，设备确定字线电压是否具有所需的电平。 响应于外部选择码信号，选择信号发生器激活每个对应于其它字线电压的选择信号之一。 外部选择代码信号指定外部指令信号代表并指定在存储器件中使用的其它字线电压。 字线电压发生器产生与所激活的选择信号相对应的字线电压。 开关电路将从字线电压发生器输出的字线电压传送到连接到外部引脚的焊盘。

公开(公告)号：US20130256956A1

公开(公告)日：2013-10-03

申请号：US13993538

申请日：2011-12-07

申请人： Hyung-Gon Kim ,  Min-Ho Lee

发明人： Hyung-Gon Kim ,  Min-Ho Lee

IPC分类号： B29C51/10 ,  B29C51/36

CPC分类号： B29C51/10 ,  B29C33/424 ,  B29C45/1418 ,  B29C45/372 ,  B29C49/04 ,  B29C51/268 ,  B29C51/36 ,  B29C2791/006 ,  B29C2791/007

摘要： Provided is a vacuum mold having a reverse solid pattern, which enables an insert sheet to be vacuum-formed, and a solid pattern to be transferred to the insert sheet. The vacuum mold having the reverse solid pattern includes: a lower mold; and a solid pattern disposed on the surface of the lower mold. The insert sheet disposed above the lower mold is adsorbed to the surface of the lower mold by vacuum pressure in order to transfer a pattern of the solid pattern to the insert sheet.

摘要翻译： 提供了具有反向固体图案的真空模具，其能够使插入片材真空成形，并且将固体图案转印到插入片材。 具有反向固体图案的真空模具包括：下模具; 以及设置在下模具的表面上的实心图案。 设置在下模具上方的插入片材通过真空压力吸附到下模具的表面，以将固体图案的图案转印到插入片材上。

公开(公告)号：US08179727B2

公开(公告)日：2012-05-15

申请号：US12265003

申请日：2008-11-05

申请人： Hyung-Gon Kim

发明人： Hyung-Gon Kim

IPC分类号： G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  G11C16/12

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main register from the memory cell during a first verifying operation; storing a data bit into the cache register from the memory cell during a second verifying operation; and transferring the data bit to the main register from the cache register.

摘要翻译： 通过用LSB编程存储器单元，在NAND闪存器件中编程多个位; 将所述LSB从所述存储器单元存储到高速缓存寄存器中; 用存储在主寄存器中的MSB对存储单元进行编程; 在第一验证操作期间将数据位从存储器单元存储到主寄存器中; 在第二验证操作期间将数据位从存储器单元存储到高速缓存寄存器中; 并将数据位从缓存寄存器传送到主寄存器。

公开(公告)号：US20110075493A1

公开(公告)日：2011-03-31

申请号：US12895350

申请日：2010-09-30

申请人： Min-Su Kim ,  Hyung-Gon Kim

发明人： Min-Su Kim ,  Hyung-Gon Kim

IPC分类号： G11C7/22

CPC分类号： G11C16/30

摘要： A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided.

摘要翻译： 非易失性存储器件包括排列成行和列的存储器单元阵列，存储器单元阵列具有与之相关联的字线。 字线电压控制器确定要提供给各个字线的字线电压的电平，并且字线电压发生器以所确定的电平产生字线电压。 还提供了相关方法。

公开(公告)号：US07783941B2

公开(公告)日：2010-08-24

申请号：US11009826

申请日：2004-12-10

申请人： Hyung-Gon Kim

发明人： Hyung-Gon Kim

IPC分类号： G11C29/00

CPC分类号： G11C29/42

摘要： A memory device includes a main memory cell array and a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array. The device further includes a parity generator configured to generate a second parity code responsive to reading of the stored data from the main memory cell array, and a comparator configured to compare the first and second parity codes. In some embodiments, the parity generator configured to generate the second parity code during a copyback operation.

摘要翻译： 存储器件包括主存储单元阵列和冗余存储单元阵列，冗余存储单元阵列被配置为存储存储在主存储单元阵列中的数据的第一奇偶校验码。 该设备还包括奇偶校验发生器，其被配置为响应于从主存储器单元阵列读取存储的数据而产生第二奇偶校验码，以及比较器，被配置为比较第一和第二奇偶校验码。 在一些实施例中，奇偶校验发生器被配置为在回拷操作期间生成第二奇偶校验码。

公开(公告)号：US20090080251A1

公开(公告)日：2009-03-26

申请号：US12265003

申请日：2008-11-05

申请人： Hyung-Gon Kim

发明人： Hyung-Gon Kim

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main register from the memory cell during a first verifying operation; storing a data bit into the cache register from the memory cell during a second verifying operation; and transferring the data bit to the main register from the cache register.

摘要翻译： 通过用LSB编程存储器单元，在NAND闪存器件中编程多个位; 将所述LSB从所述存储器单元存储到高速缓存寄存器中; 用存储在主寄存器中的MSB对存储单元进行编程; 在第一验证操作期间将数据位从存储器单元存储到主寄存器中; 在第二验证操作期间将数据位从存储器单元存储到高速缓存寄存器中; 并将数据位从缓存寄存器传送到主寄存器。

公开(公告)号：US07466597B2

公开(公告)日：2008-12-16

申请号：US11020549

申请日：2004-12-22

申请人： Hyung-Gon Kim

发明人： Hyung-Gon Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G06F11/1068 ,  G11C16/105 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2207/2236

摘要： A NAND flash memory device according to some embodiments includes a cell array, a page buffer configured to copyback read the data in the cell array, and an error detector for detecting errors that occur during the copyback reading and for generating a detection signal. Detecting errors is performed concurrently with a copyback program operation and completes before finishing a copyback program verify operation. The data stored in the page buffer may be copyback programmed when the detection signal is a pass signal. The copyback operation may end without executing the copyback program operation when the detection signal is a fail signal. Since the copyback program operation and the error detection operation are performed concurrently, the errors occurring during the copyback operation may be detected without additional time delay. Additionally, occurrence of two-bit error may be prevented because the copyback program is not executed when the fail signal is generated.

摘要翻译： 根据一些实施例的NAND闪速存储器件包括单元阵列，被配置为回读读取单元阵列中的数据的页缓冲器，以及用于检测在复印读取期间发生的错误并用于生成检测信号的错误检测器。 检测错误与拷贝程序操作同时执行，并在完成回拷程序验证操作之前完成。 当检测信号是通过信号时，存储在页面缓冲器中的数据可以被拷贝编程。 当检测信号为故障信号时，拷贝操作可能不执行复制程序操作而结束。 由于并行执行复印程序操作和错误检测操作，所以可以在没有额外的时间延迟的情况下检测在回拷操作期间发生的错误。 此外，由于在生成故障信号时不执行回拷程序，所以可以防止出现2位错误。

公开(公告)号：US07429720B2

公开(公告)日：2008-09-30

申请号：US10541578

申请日：2004-01-12

申请人： Hyung-Gon Kim

发明人： Hyung-Gon Kim

IPC分类号： H05B3/02 ,  F28D15/00

CPC分类号： F24C7/062 ,  F24C7/002 ,  F24D13/022 ,  F24H3/004 ,  F28D1/0226 ,  Y02B30/26

摘要： The present invention relates to an electric radiating pipe capable of enhancing a heating efficiency in such a manner that a mixture of a porous operation medium and a volatile operation fluid is filled in a radiation pipe, and a porous operation medium is fast heated based on a viscosity difference, and a densely filled operation fluid is phase-changed to a high temperature vapor or a high temperature liquid based on a heated operation medium. In a radiating pipe that includes a certain shaped pipe body, and a heat wire passing through to the interior of the pipe body wherein both ends of the pipe body are sealed by a plugging cap, there is provided an electric radiating pipe that includes a porous non-flammable operation medium and volatile operation fluid being mixed and being filled into the interior of the pipe body.

摘要翻译： 本发明涉及一种能够提高加热效率的电辐射管，使得多孔操作介质和挥发性操作流体的混合物填充在辐射管中，并且多孔操作介质基于 粘度差和密集填充的操作流体基于加热的操作介质相变为高温蒸气或高温液体。 在包括一定形状的管体的辐射管中，以及通过管体内部的热丝，其中管体的两端由堵塞帽密封，设置有电气辐射管，其包括多孔 非易燃操作介质和挥发性操作流体混合并填充到管体的内部。

公开(公告)号：US20070067705A1

公开(公告)日：2007-03-22

申请号：US11430867

申请日：2006-05-10

申请人： Hyung-Gon Kim

发明人： Hyung-Gon Kim

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/11 ,  G06F11/1068

摘要： A NAND flash memory device performing an error detecting and data reloading operation during a copy back program operation is provided. The device includes a cell array having a plurality of planes and a parity cell array having a plurality of parity planes. Each of the parity planes stores a parity of each of the planes. Additionally, the device includes a parity generating and parity column selecting circuit generating a new parity about reloaded data from an outside during a copy back program operation, and storing the new parity on a parity plane corresponding to a plane on which the reloaded data is stored.

摘要翻译： 提供了在复制回程序操作期间执行错误检测和数据重新加载操作的NAND快闪存储器件。 该装置包括具有多个平面的单元阵列和具有多个奇偶校验平面的奇偶校验单元阵列。 每个奇偶校验平面存储每个平面的奇偶校验。 此外，该装置包括奇偶校验生成和奇偶校验列选择电路，其在复制回程序操作期间从外部产生关于重新加载的数据的新奇偶校验，并将新的奇偶校验存储在对应于重新加载的数据被存储的平面的奇偶校验平面上 。

公开(公告)号：US20060053361A1

公开(公告)日：2006-03-09

申请号：US11009826

申请日：2004-12-10

申请人： Hyung-Gon Kim

发明人： Hyung-Gon Kim

IPC分类号： G11C29/00

CPC分类号： G11C29/42

摘要： A memory device includes a main memory cell array and a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array. The device further includes a parity generator configured to generate a second parity code responsive to reading of the stored data from the main memory cell array, and a comparator configured to compare the first and second parity codes. The parity generator may be configured to generate the second parity code during a copyback operation.

摘要翻译： 存储器件包括主存储单元阵列和冗余存储单元阵列，冗余存储单元阵列被配置为存储存储在主存储单元阵列中的数据的第一奇偶校验码。 该设备还包括奇偶校验发生器，其被配置为响应于从主存储器单元阵列读取存储的数据而产生第二奇偶校验码，以及比较器，被配置为比较第一和第二奇偶校验码。 奇偶校验生成器可以被配置为在回拷操作期间生成第二奇偶校验码。